llvm-mirror/test/CodeGen/ARM/2009-05-05-DAGCombineBug.ll

; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -mattr=+v6
; PR4166

	%"byte[]" = type { i32, i8* }
	%tango.time.Time.Time = type { i64 }

define fastcc void @t() {
entry:
	%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null)		; <i1> [#uses=0]
	ret void
}
Correct some bogus target triples. llvm-svn: 103265 2010-05-07 19:03:48 +02:00			`; RUN: llc < %s -mtriple=arm-unknown-linux-gnueabi -mattr=+v6`
Do not use register as base ptr of pre- and post- inc/dec load / store nodes. llvm-svn: 71098 2009-05-06 20:25:01 +02:00			`; PR4166`

			`%"byte[]" = type { i32, i8* }`
			`%tango.time.Time.Time = type { i64 }`

			`define fastcc void @t() {`
			`entry:`
			`%tmp28 = call fastcc i1 null(i32* null, %"byte[]" undef, %"byte[]" undef, %tango.time.Time.Time* byval null) ; <i1> [#uses=0]`
			`ret void`
			`}`