2013-06-26 20:48:17 +02:00
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; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
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2013-07-14 08:24:09 +02:00
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; CHECK-LABEL: mul5_32:
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2013-06-26 20:48:17 +02:00
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; CHECK: sll $[[R0:[0-9]+]], $4, 2
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; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
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define i32 @mul5_32(i32 %a) {
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entry:
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%mul = mul nsw i32 %a, 5
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ret i32 %mul
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}
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2013-07-14 08:24:09 +02:00
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; CHECK-LABEL: mul27_32:
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2013-06-26 20:48:17 +02:00
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; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
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; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
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; CHECK: subu ${{[0-9]+}}, $[[R2]], $[[R1]]
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define i32 @mul27_32(i32 %a) {
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entry:
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%mul = mul nsw i32 %a, 27
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ret i32 %mul
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}
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2013-07-14 08:24:09 +02:00
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; CHECK-LABEL: muln2147483643_32:
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2013-06-26 20:48:17 +02:00
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; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
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; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
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; CHECK: addu ${{[0-9]+}}, $[[R2]], $[[R1]]
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define i32 @muln2147483643_32(i32 %a) {
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entry:
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%mul = mul nsw i32 %a, -2147483643
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ret i32 %mul
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}
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2013-07-14 08:24:09 +02:00
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; CHECK64-LABEL: muln9223372036854775805_64:
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2013-07-01 22:18:58 +02:00
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; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
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; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
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; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
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; CHECK64: daddu ${{[0-9]+}}, $[[R2]], $[[R1]]
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2013-06-26 20:48:17 +02:00
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define i64 @muln9223372036854775805_64(i64 %a) {
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entry:
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%mul = mul nsw i64 %a, -9223372036854775805
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ret i64 %mul
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}
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