llvm-mirror/test/CodeGen/X86/2012-05-19-avx2-store.ll

; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx2 | FileCheck %s

define void @double_save(<4 x i32>* %Ap, <4 x i32>* %Bp, <8 x i32>* %P) nounwind ssp {
entry:
  ; CHECK: vmovaps
  ; CHECK: vinsertf128 $1, ([[A0:%rdi|%rsi]]),
  ; CHECK: vmovups
  %A = load <4 x i32>* %Ap
  %B = load <4 x i32>* %Bp
  %Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  store <8 x i32> %Z, <8 x i32>* %P, align 16
  ret void
}
On Haswell, perfer storing YMM registers using a single instruction. llvm-svn: 157129 2012-05-19 22:30:08 +02:00			`; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx2 \| FileCheck %s`

			`define void @double_save(<4 x i32>* %Ap, <4 x i32>* %Bp, <8 x i32>* %P) nounwind ssp {`
			`entry:`
			`; CHECK: vmovaps`
X86 Peephole: fold loads to the source register operand if possible. Machine CSE and other optimizations can remove instructions so folding is possible at peephole while not possible at ISel. This patch is a rework of r160919 and was tested on clang self-host on my local machine. rdar://10554090 and rdar://11873276 llvm-svn: 161152 2012-08-02 02:56:42 +02:00			`; CHECK: vinsertf128 $1, ([[A0:%rdi\|%rsi]]),`
On Haswell, perfer storing YMM registers using a single instruction. llvm-svn: 157129 2012-05-19 22:30:08 +02:00			`; CHECK: vmovups`
			`%A = load <4 x i32>* %Ap`
			`%B = load <4 x i32>* %Bp`
			`%Z = shufflevector <4 x i32>%A, <4 x i32>%B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>`
			`store <8 x i32> %Z, <8 x i32>* %P, align 16`
			`ret void`
			`}`