2012-02-18 13:03:15 +01:00
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//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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2004-08-17 06:55:41 +02:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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2012-03-17 19:46:09 +01:00
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#include "PPCRegisterInfo.h"
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2005-10-15 01:51:18 +02:00
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#include "PPC.h"
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2012-12-03 17:50:05 +01:00
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#include "PPCFrameLowering.h"
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2005-10-15 01:45:43 +02:00
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#include "PPCInstrBuilder.h"
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2006-11-16 23:43:37 +01:00
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#include "PPCMachineFunctionInfo.h"
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2006-07-11 02:48:23 +02:00
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#include "PPCSubtarget.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-01-26 22:22:28 +01:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2007-12-31 05:13:23 +01:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-03-03 23:19:16 +01:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/CodeGen/ValueTypes.h"
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2013-01-02 12:36:10 +01:00
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Type.h"
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2004-09-02 00:55:40 +02:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2009-07-08 22:53:28 +02:00
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#include "llvm/Support/ErrorHandling.h"
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2005-11-06 10:00:38 +01:00
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#include "llvm/Support/MathExtras.h"
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2009-07-08 22:53:28 +02:00
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#include "llvm/Support/raw_ostream.h"
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2012-12-03 17:50:05 +01:00
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2004-08-17 06:55:41 +02:00
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#include <cstdlib>
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2011-06-27 20:32:37 +02:00
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#define GET_REGINFO_TARGET_DESC
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2011-06-24 03:44:41 +02:00
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#include "PPCGenRegisterInfo.inc"
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2004-08-17 06:55:41 +02:00
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2010-04-15 19:20:57 +02:00
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using namespace llvm;
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2006-11-14 00:36:35 +01:00
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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2011-07-18 22:57:22 +02:00
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: PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
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ST.isPPC64() ? 0 : 1,
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ST.isPPC64() ? 0 : 1),
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2013-02-24 18:34:50 +01:00
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Subtarget(ST), TII(tii) {
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2005-04-22 01:30:14 +02:00
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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2004-08-17 06:55:41 +02:00
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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2005-10-18 02:28:58 +02:00
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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2007-09-08 00:01:02 +02:00
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
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ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
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ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
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2013-03-31 03:58:02 +02:00
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
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2004-08-17 06:55:41 +02:00
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}
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2009-02-06 18:43:24 +01:00
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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2009-07-29 22:31:52 +02:00
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const TargetRegisterClass *
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2012-05-08 00:10:26 +02:00
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PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
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const {
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2013-04-06 21:30:30 +02:00
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// Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
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// when it checks for ZERO folding.
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Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
llvm-svn: 177423
2013-03-19 19:51:05 +01:00
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if (Kind == 1) {
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if (Subtarget.isPPC64())
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return &PPC::G8RC_NOX0RegClass;
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return &PPC::GPRC_NOR0RegClass;
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}
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2009-02-06 18:43:24 +01:00
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if (Subtarget.isPPC64())
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return &PPC::G8RCRegClass;
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2009-07-29 22:31:52 +02:00
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return &PPC::GPRCRegClass;
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2009-02-06 18:43:24 +01:00
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}
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2012-03-04 04:33:22 +01:00
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const uint16_t*
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 03:14:50 +02:00
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2012-03-06 17:41:49 +01:00
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if (Subtarget.isDarwinABI())
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return Subtarget.isPPC64() ? CSR_Darwin64_SaveList :
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CSR_Darwin32_SaveList;
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2009-08-15 13:54:46 +02:00
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2012-03-06 17:41:49 +01:00
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return Subtarget.isPPC64() ? CSR_SVR464_SaveList : CSR_SVR432_SaveList;
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}
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2009-08-15 13:54:46 +02:00
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2012-09-16 20:10:23 +02:00
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const uint32_t*
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2012-03-06 17:41:49 +01:00
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PPCRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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2009-07-03 08:47:08 +02:00
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if (Subtarget.isDarwinABI())
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2012-03-06 17:41:49 +01:00
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return Subtarget.isPPC64() ? CSR_Darwin64_RegMask :
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CSR_Darwin32_RegMask;
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2009-08-15 13:54:46 +02:00
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2012-03-06 17:41:49 +01:00
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return Subtarget.isPPC64() ? CSR_SVR464_RegMask : CSR_SVR432_RegMask;
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2006-05-18 02:12:58 +02:00
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}
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2013-03-21 22:37:52 +01:00
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const uint32_t*
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PPCRegisterInfo::getNoPreservedMask() const {
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// The naming here is inverted: The CSR_NoRegs_Altivec has the
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// Altivec registers masked so that they're not saved and restored around
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// instructions with this preserved mask.
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if (!Subtarget.hasAltivec())
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return CSR_NoRegs_Altivec_RegMask;
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2013-03-27 01:02:20 +01:00
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if (Subtarget.isDarwin())
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return CSR_NoRegs_Darwin_RegMask;
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2013-03-21 22:37:52 +01:00
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return CSR_NoRegs_RegMask;
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}
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2007-02-19 22:49:54 +01:00
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BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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2011-01-10 13:39:04 +01:00
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const PPCFrameLowering *PPCFI =
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static_cast<const PPCFrameLowering*>(MF.getTarget().getFrameLowering());
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2010-11-18 22:19:35 +01:00
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Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
llvm-svn: 177423
2013-03-19 19:51:05 +01:00
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// The ZERO register is not really a register, but the representation of r0
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// when used in instructions that treat r0 as the constant 0.
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Reserved.set(PPC::ZERO);
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2013-03-22 00:45:03 +01:00
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Reserved.set(PPC::ZERO8);
|
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
llvm-svn: 177423
2013-03-19 19:51:05 +01:00
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2013-03-21 20:03:19 +01:00
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// The FP register is also not really a register, but is the representation
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// of the frame pointer register used by ISD::FRAMEADDR.
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Reserved.set(PPC::FP);
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Reserved.set(PPC::FP8);
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2007-02-19 22:49:54 +01:00
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Reserved.set(PPC::R1);
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Reserved.set(PPC::LR);
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2008-03-03 23:19:16 +01:00
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Reserved.set(PPC::LR8);
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2008-10-29 19:26:45 +01:00
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Reserved.set(PPC::RM);
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2008-03-03 23:19:16 +01:00
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2009-07-03 08:45:56 +02:00
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// The SVR4 ABI reserves r2 and r13
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2009-07-03 08:47:08 +02:00
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if (Subtarget.isSVR4ABI()) {
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2009-07-03 08:45:56 +02:00
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Reserved.set(PPC::R2); // System-reserved register
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Reserved.set(PPC::R13); // Small Data Area pointer register
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}
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2009-08-15 13:54:46 +02:00
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// On PPC64, r13 is the thread pointer. Never allocate this register.
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2007-02-19 22:49:54 +01:00
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if (Subtarget.isPPC64()) {
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Reserved.set(PPC::R13);
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2008-03-03 23:19:16 +01:00
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Reserved.set(PPC::X1);
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Reserved.set(PPC::X13);
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2013-03-19 09:09:38 +01:00
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if (PPCFI->needsFP(MF))
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Reserved.set(PPC::X31);
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2009-08-15 13:54:46 +02:00
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// The 64-bit SVR4 ABI reserves r2 for the TOC pointer.
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if (Subtarget.isSVR4ABI()) {
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Reserved.set(PPC::X2);
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}
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2007-02-19 22:49:54 +01:00
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}
|
2008-03-03 23:19:16 +01:00
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2010-12-18 20:53:14 +01:00
|
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if (PPCFI->needsFP(MF))
|
2007-02-19 22:49:54 +01:00
|
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Reserved.set(PPC::R31);
|
2008-03-03 23:19:16 +01:00
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2007-02-19 22:49:54 +01:00
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return Reserved;
|
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}
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|
2011-11-22 17:21:04 +01:00
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unsigned
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PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
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const unsigned DefaultSafety = 1;
|
|
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switch (RC->getID()) {
|
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default:
|
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return 0;
|
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
llvm-svn: 177423
2013-03-19 19:51:05 +01:00
|
|
|
case PPC::G8RC_NOX0RegClassID:
|
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case PPC::GPRC_NOR0RegClassID:
|
2011-11-22 17:21:04 +01:00
|
|
|
case PPC::G8RCRegClassID:
|
|
|
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case PPC::GPRCRegClassID: {
|
|
|
|
unsigned FP = TFI->hasFP(MF) ? 1 : 0;
|
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return 32 - FP - DefaultSafety;
|
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}
|
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case PPC::F8RCRegClassID:
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case PPC::F4RCRegClassID:
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case PPC::VRRCRegClassID:
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return 32 - DefaultSafety;
|
2011-12-05 18:54:17 +01:00
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case PPC::CRRCRegClassID:
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return 8 - DefaultSafety;
|
2011-11-22 17:21:04 +01:00
|
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}
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}
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|
2004-08-17 06:55:41 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Stack Frame Processing methods
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|
//===----------------------------------------------------------------------===//
|
|
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|
2008-03-03 23:19:16 +01:00
|
|
|
/// lowerDynamicAlloc - Generate the code for allocating an object in the
|
2006-11-16 23:43:37 +01:00
|
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|
/// current frame. The sequence of code with be in the general form
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///
|
2009-03-03 03:55:14 +01:00
|
|
|
/// addi R0, SP, \#frameSize ; get the address of the previous frame
|
2006-11-16 23:43:37 +01:00
|
|
|
/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
|
2009-03-03 03:55:14 +01:00
|
|
|
/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
|
2006-11-16 23:43:37 +01:00
|
|
|
///
|
2013-03-23 20:36:47 +01:00
|
|
|
void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II;
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
// Get the basic block's function.
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
// Get the frame info.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Determine whether 64-bit pointers are used.
|
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2009-02-13 03:27:39 +01:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
2006-11-16 23:43:37 +01:00
|
|
|
|
2007-01-25 23:48:25 +01:00
|
|
|
// Get the maximum call stack size.
|
2006-11-16 23:43:37 +01:00
|
|
|
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
|
|
|
|
// Get the total frame size.
|
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
// Get stack alignments.
|
2011-01-10 13:39:04 +01:00
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
|
2006-11-16 23:43:37 +01:00
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2010-07-30 23:09:48 +02:00
|
|
|
if (MaxAlign > TargetAlign)
|
|
|
|
report_fatal_error("Dynamic alloca with large aligns not supported");
|
2006-11-16 23:43:37 +01:00
|
|
|
|
|
|
|
// Determine the previous frame's address. If FrameSize can't be
|
|
|
|
// represented as 16 bits or we need special alignment, then we load the
|
|
|
|
// previous frame's address from 0(SP). Why not do an addis of the hi?
|
|
|
|
// Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
|
|
|
|
// Constructing the constant and adding would take 3 instructions.
|
|
|
|
// Fortunately, a frame greater than 32K is rare.
|
2008-03-03 23:19:16 +01:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
2013-03-14 21:21:47 +01:00
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2010-03-29 23:13:41 +02:00
|
|
|
if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) {
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addReg(PPC::R31)
|
|
|
|
.addImm(FrameSize);
|
|
|
|
} else if (LP64) {
|
2013-03-12 15:12:16 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
|
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::X1);
|
2006-11-16 23:43:37 +01:00
|
|
|
} else {
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::R1);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// Grow the stack and update the stack pointer link, then determine the
|
|
|
|
// address of new allocated space.
|
2006-11-16 23:43:37 +01:00
|
|
|
if (LP64) {
|
2013-03-12 15:12:16 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
|
|
|
|
.addReg(Reg, RegState::Kill)
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 23:19:16 +01:00
|
|
|
if (!MI.getOperand(1).isKill())
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 23:19:16 +01:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize)
|
2009-05-13 23:33:08 +02:00
|
|
|
.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
|
2006-11-16 23:43:37 +01:00
|
|
|
} else {
|
2012-06-19 04:34:32 +02:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
|
2009-05-13 23:33:08 +02:00
|
|
|
.addReg(Reg, RegState::Kill)
|
2012-06-19 04:34:32 +02:00
|
|
|
.addReg(PPC::R1)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
if (!MI.getOperand(1).isKill())
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 23:19:16 +01:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
2009-02-13 03:27:39 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize)
|
2009-05-13 23:33:08 +02:00
|
|
|
.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
|
2006-11-16 23:43:37 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Discard the DYNALLOC instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
|
|
|
|
/// reserving a whole register (R0), we scrounge for one here. This generates
|
|
|
|
/// code like this:
|
|
|
|
///
|
|
|
|
/// mfcr rA ; Move the conditional register into GPR rA.
|
|
|
|
/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
|
|
|
|
/// stw rA, FI ; Store rA to the frame.
|
|
|
|
///
|
|
|
|
void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
|
2013-03-23 20:36:47 +01:00
|
|
|
unsigned FrameIndex) const {
|
2008-03-03 23:19:16 +01:00
|
|
|
// Get the instruction.
|
2011-12-06 21:55:36 +01:00
|
|
|
MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
|
2008-03-03 23:19:16 +01:00
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 19:57:22 +01:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2009-02-13 03:27:39 +01:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2011-06-17 17:21:10 +02:00
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2013-03-26 19:57:22 +01:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2011-12-10 05:50:53 +01:00
|
|
|
unsigned SrcReg = MI.getOperand(0).getReg();
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2008-03-05 00:27:33 +01:00
|
|
|
// We need to store the CR in the low 4-bits of the saved value. First, issue
|
2010-05-20 19:48:26 +02:00
|
|
|
// an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
|
2011-12-07 07:34:06 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFCR8pseud : PPC::MFCRpseud), Reg)
|
2010-05-20 19:48:26 +02:00
|
|
|
.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
|
2008-03-05 00:27:33 +01:00
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// If the saved register wasn't CR0, shift the bits left so that they are in
|
|
|
|
// CR0's slot.
|
2013-03-26 19:57:22 +01:00
|
|
|
if (SrcReg != PPC::CR0) {
|
|
|
|
unsigned Reg1 = Reg;
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// rlwinm rA, rA, ShiftBits, 0, 31.
|
2011-12-07 07:34:06 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
2013-03-26 19:57:22 +01:00
|
|
|
.addReg(Reg1, RegState::Kill)
|
2013-03-26 21:08:20 +01:00
|
|
|
.addImm(getEncodingValue(SrcReg) * 4)
|
2008-03-03 23:19:16 +01:00
|
|
|
.addImm(0)
|
|
|
|
.addImm(31);
|
2013-03-26 19:57:22 +01:00
|
|
|
}
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2011-06-17 17:21:10 +02:00
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW))
|
2013-03-28 04:38:16 +01:00
|
|
|
.addReg(Reg, RegState::Kill),
|
2008-03-03 23:19:16 +01:00
|
|
|
FrameIndex);
|
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2011-12-06 21:55:36 +01:00
|
|
|
void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
|
2013-03-23 20:36:47 +01:00
|
|
|
unsigned FrameIndex) const {
|
2011-12-06 21:55:36 +01:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 19:57:22 +01:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2011-12-06 21:55:36 +01:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2011-12-10 05:50:53 +01:00
|
|
|
bool LP64 = Subtarget.isPPC64();
|
2013-03-26 19:57:22 +01:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
2011-12-06 21:55:36 +01:00
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
assert(MI.definesRegister(DestReg) &&
|
|
|
|
"RESTORE_CR does not define its destination");
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
|
|
|
|
Reg), FrameIndex);
|
|
|
|
|
|
|
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
|
|
// in the right CR's slot.
|
|
|
|
if (DestReg != PPC::CR0) {
|
2013-03-26 19:57:22 +01:00
|
|
|
unsigned Reg1 = Reg;
|
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
|
|
|
|
|
2013-03-26 21:08:20 +01:00
|
|
|
unsigned ShiftBits = getEncodingValue(DestReg)*4;
|
2011-12-06 21:55:36 +01:00
|
|
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
2012-01-17 00:22:50 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
|
2013-03-26 19:57:22 +01:00
|
|
|
.addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
|
2011-12-06 21:55:36 +01:00
|
|
|
.addImm(31);
|
|
|
|
}
|
|
|
|
|
2011-12-07 07:34:06 +01:00
|
|
|
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTCRF8 : PPC::MTCRF), DestReg)
|
2013-03-26 19:57:22 +01:00
|
|
|
.addReg(Reg, RegState::Kill);
|
2011-12-06 21:55:36 +01:00
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2013-03-21 20:03:21 +01:00
|
|
|
void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II,
|
2013-03-23 20:36:47 +01:00
|
|
|
unsigned FrameIndex) const {
|
2013-03-21 20:03:21 +01:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 19:57:22 +01:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-03-21 20:03:21 +01:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2013-03-26 19:57:22 +01:00
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
|
2013-03-21 20:03:21 +01:00
|
|
|
unsigned SrcReg = MI.getOperand(0).getReg();
|
|
|
|
|
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
|
|
|
|
.addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW))
|
2013-03-28 04:38:16 +01:00
|
|
|
.addReg(Reg, RegState::Kill),
|
2013-03-21 20:03:21 +01:00
|
|
|
FrameIndex);
|
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
|
|
|
void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
|
2013-03-23 20:36:47 +01:00
|
|
|
unsigned FrameIndex) const {
|
2013-03-21 20:03:21 +01:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2013-03-26 19:57:22 +01:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2013-03-21 20:03:21 +01:00
|
|
|
DebugLoc dl = MI.getDebugLoc();
|
|
|
|
|
2013-03-26 19:57:22 +01:00
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC);
|
2013-03-21 20:03:21 +01:00
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
assert(MI.definesRegister(DestReg) &&
|
|
|
|
"RESTORE_VRSAVE does not define its destination");
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
|
|
|
|
Reg), FrameIndex);
|
|
|
|
|
|
|
|
BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
|
2013-03-26 19:57:22 +01:00
|
|
|
.addReg(Reg, RegState::Kill);
|
2013-03-21 20:03:21 +01:00
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2012-09-12 16:47:47 +02:00
|
|
|
bool
|
|
|
|
PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
|
|
|
|
unsigned Reg, int &FrameIdx) const {
|
|
|
|
|
|
|
|
// For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
|
|
|
|
// ABI, return true to prevent allocating an additional frame slot.
|
|
|
|
// For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
|
2013-02-24 18:34:50 +01:00
|
|
|
// is arbitrary and will be subsequently ignored. For 32-bit, we have
|
|
|
|
// previously created the stack slot if needed, so return its FrameIdx.
|
2012-09-12 16:47:47 +02:00
|
|
|
if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
|
2013-02-24 18:34:50 +01:00
|
|
|
if (Subtarget.isPPC64())
|
2012-09-12 16:47:47 +02:00
|
|
|
FrameIdx = 0;
|
2013-02-24 18:34:50 +01:00
|
|
|
else {
|
|
|
|
const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
FrameIdx = FI->getCRSpillFrameIndex();
|
2012-09-12 16:47:47 +02:00
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2010-08-27 01:32:16 +02:00
|
|
|
void
|
2009-10-07 19:12:56 +02:00
|
|
|
PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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2013-01-31 21:02:54 +01:00
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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2007-05-01 11:13:03 +02:00
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assert(SPAdj == 0 && "Unexpected");
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2006-11-16 23:43:37 +01:00
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// Get the instruction.
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2004-08-17 06:55:41 +02:00
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MachineInstr &MI = *II;
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2006-11-16 23:43:37 +01:00
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// Get the instruction's basic block.
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2004-08-17 06:55:41 +02:00
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MachineBasicBlock &MBB = *MI.getParent();
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2006-11-16 23:43:37 +01:00
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// Get the basic block's function.
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2004-08-17 06:55:41 +02:00
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MachineFunction &MF = *MBB.getParent();
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2006-11-16 23:43:37 +01:00
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// Get the frame info.
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MachineFrameInfo *MFI = MF.getFrameInfo();
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2011-01-10 13:39:04 +01:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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2009-02-13 03:27:39 +01:00
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DebugLoc dl = MI.getDebugLoc();
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2005-04-22 01:30:14 +02:00
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2006-11-16 23:43:37 +01:00
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// Take into account whether it's an add or mem instruction
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2013-01-31 21:02:54 +01:00
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unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
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2010-02-09 20:54:29 +01:00
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if (MI.isInlineAsm())
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2013-01-31 21:02:54 +01:00
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OffsetOperandNo = FIOperandNum-1;
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2008-03-03 23:19:16 +01:00
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2006-11-16 23:43:37 +01:00
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// Get the frame index.
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2013-01-31 21:02:54 +01:00
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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2008-03-03 23:19:16 +01:00
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2006-11-16 23:43:37 +01:00
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// Get the frame pointer save index. Users of this index are primarily
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// DYNALLOC instructions.
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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int FPSI = FI->getFramePointerSaveIndex();
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// Get the instruction opcode.
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unsigned OpC = MI.getOpcode();
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// Special case for dynamic alloca.
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if (FPSI && FrameIndex == FPSI &&
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(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
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2013-03-23 20:36:47 +01:00
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lowerDynamicAlloc(II);
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2010-08-27 01:32:16 +02:00
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return;
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2008-03-03 23:19:16 +01:00
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}
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2013-03-21 20:03:21 +01:00
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// Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
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2013-03-12 15:12:16 +01:00
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if (OpC == PPC::SPILL_CR) {
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2013-03-23 20:36:47 +01:00
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lowerCRSpilling(II, FrameIndex);
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2013-03-12 15:12:16 +01:00
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return;
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} else if (OpC == PPC::RESTORE_CR) {
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2013-03-23 20:36:47 +01:00
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lowerCRRestore(II, FrameIndex);
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2013-03-12 15:12:16 +01:00
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return;
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2013-03-21 20:03:21 +01:00
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} else if (OpC == PPC::SPILL_VRSAVE) {
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2013-03-23 20:36:47 +01:00
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lowerVRSAVESpilling(II, FrameIndex);
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2013-03-21 20:03:21 +01:00
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return;
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} else if (OpC == PPC::RESTORE_VRSAVE) {
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2013-03-23 20:36:47 +01:00
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lowerVRSAVERestore(II, FrameIndex);
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2013-03-21 20:03:21 +01:00
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return;
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2011-12-06 21:55:36 +01:00
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}
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2004-08-17 06:55:41 +02:00
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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2011-12-07 07:34:02 +01:00
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bool is64Bit = Subtarget.isPPC64();
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2013-01-31 21:02:54 +01:00
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MI.getOperand(FIOperandNum).ChangeToRegister(TFI->hasFP(MF) ?
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2011-12-07 07:34:02 +01:00
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(is64Bit ? PPC::X31 : PPC::R31) :
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(is64Bit ? PPC::X1 : PPC::R1),
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2007-10-16 20:00:18 +02:00
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false);
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2004-08-17 06:55:41 +02:00
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2006-06-27 20:55:49 +02:00
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// Figure out if the offset in the instruction is shifted right two bits. This
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// is true for instructions like "STD", which the machine implicitly adds two
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// low zeros to.
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bool isIXAddr = false;
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2006-11-16 23:43:37 +01:00
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switch (OpC) {
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2006-06-27 20:55:49 +02:00
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case PPC::LWA:
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case PPC::LD:
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case PPC::STD:
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isIXAddr = true;
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break;
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}
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2013-03-17 05:43:44 +01:00
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2013-03-31 16:43:31 +02:00
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// If the instruction is not present in ImmToIdxMap, then it has no immediate
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// form (and must be r+r).
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2013-04-01 19:02:06 +02:00
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bool noImmForm = !MI.isInlineAsm() && !ImmToIdxMap.count(OpC);
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2013-03-17 05:43:44 +01:00
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2004-08-17 06:55:41 +02:00
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// Now add the frame object offset to the offset from r1.
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2006-11-16 23:43:37 +01:00
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int Offset = MFI->getObjectOffset(FrameIndex);
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2006-06-27 20:55:49 +02:00
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if (!isIXAddr)
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2007-12-30 21:49:49 +01:00
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Offset += MI.getOperand(OffsetOperandNo).getImm();
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2006-06-27 20:55:49 +02:00
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else
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2007-12-30 21:49:49 +01:00
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Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
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2004-08-17 06:55:41 +02:00
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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2010-04-29 21:32:19 +02:00
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// Naked functions have stack size 0, although getStackSize may not reflect that
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// because we didn't call all the pieces that compute it for naked functions.
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2012-12-30 11:32:01 +01:00
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if (!MF.getFunction()->getAttributes().
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hasAttribute(AttributeSet::FunctionIndex, Attribute::Naked))
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2010-04-29 21:32:19 +02:00
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Offset += MFI->getStackSize();
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2005-04-22 01:30:14 +02:00
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2007-11-27 23:14:42 +01:00
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// If we can, encode the offset directly into the instruction. If this is a
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// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
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// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
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// clear can be encoded. This is extremely uncommon, because normally you
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// only "std" to a stack slot that is at least 4-byte aligned, but it can
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// happen in invalid code.
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2012-03-22 06:28:19 +01:00
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if (OpC == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
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2013-03-17 05:43:44 +01:00
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(!noImmForm &&
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isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0))) {
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2007-11-27 23:14:42 +01:00
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if (isIXAddr)
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2007-10-16 20:00:18 +02:00
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Offset >>= 2; // The actual encoded value has the low two bits zero.
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MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
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2010-08-27 01:32:16 +02:00
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return;
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2007-11-27 23:14:42 +01:00
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}
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2008-03-03 23:19:16 +01:00
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// The offset doesn't fit into a single register, scavenge one to build the
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// offset in.
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2013-03-12 15:12:16 +01:00
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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2013-03-26 19:57:20 +01:00
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const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
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unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
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SReg = MF.getRegInfo().createVirtualRegister(RC);
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2008-03-03 23:19:16 +01:00
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// Insert a set of rA with the full offset value before the ld, st, or add
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2013-03-26 19:57:20 +01:00
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
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2008-03-03 23:19:16 +01:00
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.addImm(Offset >> 16);
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2011-12-07 07:34:02 +01:00
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BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
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2013-03-26 19:57:20 +01:00
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.addReg(SRegHi, RegState::Kill)
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2008-03-03 23:19:16 +01:00
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.addImm(Offset);
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// Convert into indexed form of the instruction:
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//
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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2007-11-27 23:14:42 +01:00
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unsigned OperandBase;
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2008-03-03 23:19:16 +01:00
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2013-03-17 05:43:44 +01:00
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if (noImmForm)
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OperandBase = 1;
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else if (OpC != TargetOpcode::INLINEASM) {
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2007-11-27 23:14:42 +01:00
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assert(ImmToIdxMap.count(OpC) &&
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
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2008-01-11 19:10:50 +01:00
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MI.setDesc(TII.get(NewOpcode));
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2007-11-27 23:14:42 +01:00
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OperandBase = 1;
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2007-10-16 20:00:18 +02:00
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} else {
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2007-11-27 23:14:42 +01:00
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OperandBase = OffsetOperandNo;
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2004-08-17 06:55:41 +02:00
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}
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2010-08-27 01:32:16 +02:00
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2013-01-31 21:02:54 +01:00
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unsigned StackReg = MI.getOperand(FIOperandNum).getReg();
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2007-11-27 23:14:42 +01:00
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MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
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2011-12-30 01:34:00 +01:00
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MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true);
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2004-08-17 06:55:41 +02:00
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}
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2009-11-12 21:49:22 +01:00
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unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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2011-01-10 13:39:04 +01:00
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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2010-11-18 22:19:35 +01:00
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2006-11-11 20:05:28 +01:00
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if (!Subtarget.isPPC64())
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2010-11-18 22:19:35 +01:00
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return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
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2006-11-11 20:05:28 +01:00
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else
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2010-11-18 22:19:35 +01:00
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return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
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2006-04-07 18:34:46 +02:00
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}
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2007-02-21 23:54:50 +01:00
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unsigned PPCRegisterInfo::getEHExceptionRegister() const {
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return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
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}
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unsigned PPCRegisterInfo::getEHHandlerRegister() const {
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return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
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}
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