llvm-mirror/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding"

# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
# A8.6.89 LSL (register): Inst{7-4} = 0b0001
0x93 0x42 0xa0 0xd1
Convert the uses of '\|&' to use '2>&1 \|' instead, which works on old versions of Bash. In addition, I can back out the change to the lit built-in shell test runner to support this. This should fix the majority of fallout on Darwin, but I suspect there will be a few straggling issues. llvm-svn: 159544 2012-07-02 20:37:59 +02:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 \| grep "invalid instruction encoding"`
ARM disassembler was erroneously accepting an invalid LSL instruction. For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941 2011-04-05 23:49:44 +02:00
			`# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144 2011-08-09 22:55:18 +02:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
ARM disassembler was erroneously accepting an invalid LSL instruction. For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 llvm-svn: 128941 2011-04-05 23:49:44 +02:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 0: 1\| 0: 0: 0: 1\| 1: 0: 1: 0\| 0: 0: 0: 0\| 0: 1: 0: 0\| 0: 0: 1: 0\| 1: 0: 0: 1\| 0: 0: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
			`# A8.6.89 LSL (register): Inst{7-4} = 0b0001`
			`0x93 0x42 0xa0 0xd1`