llvm-mirror/test/CodeGen/AArch64/arm64-zext.ll

; RUN: llc < %s -march=arm64 | FileCheck %s

define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: foo:
; CHECK: add w0, w1, w0
; CHECK: ret
  %add = add i32 %b, %a
  %conv = zext i32 %add to i64
  ret i64 %conv
}
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090 2014-03-29 11:18:08 +01:00			`; RUN: llc < %s -march=arm64 \| FileCheck %s`

			`define i64 @foo(i32 %a, i32 %b) nounwind readnone ssp {`
			`entry:`
			`; CHECK-LABEL: foo:`
			`; CHECK: add w0, w1, w0`
			`; CHECK: ret`
			`%add = add i32 %b, %a`
			`%conv = zext i32 %add to i64`
			`ret i64 %conv`
			`}`