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llvm-mirror/test/CodeGen/AArch64/arm64-fmadd.ll

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ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
; RUN: llc -march=arm64 < %s | FileCheck %s
define float @fma32(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fma32:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmadd s0, s0, s1, s2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
ret float %0
}
define float @fnma32(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fnma32:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fnmadd s0, s0, s1, s2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %c)
%mul = fmul float %0, -1.000000e+00
ret float %mul
}
define float @fms32(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fms32:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmsub s0, s0, s1, s2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%mul = fmul float %b, -1.000000e+00
%0 = tail call float @llvm.fma.f32(float %a, float %mul, float %c)
ret float %0
}
ARM64: add more patterns for commuted fmsub operations. llvm-svn: 205206
2014-03-31 17:46:34 +02:00
define float @fms32_com(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fms32_com:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmsub s0, s1, s0, s2
ARM64: add more patterns for commuted fmsub operations. llvm-svn: 205206
2014-03-31 17:46:34 +02:00
%mul = fmul float %b, -1.000000e+00
%0 = tail call float @llvm.fma.f32(float %mul, float %a, float %c)
ret float %0
}
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
define float @fnms32(float %a, float %b, float %c) nounwind readnone ssp {
entry:
; CHECK-LABEL: fnms32:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fnmsub s0, s0, s1, s2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%mul = fmul float %c, -1.000000e+00
%0 = tail call float @llvm.fma.f32(float %a, float %b, float %mul)
ret float %0
}
define double @fma64(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fma64:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmadd d0, d0, d1, d2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
entry:
%0 = tail call double @llvm.fma.f64(double %a, double %b, double %c)
ret double %0
}
define double @fnma64(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fnma64:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fnmadd d0, d0, d1, d2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
entry:
%0 = tail call double @llvm.fma.f64(double %a, double %b, double %c)
%mul = fmul double %0, -1.000000e+00
ret double %mul
}
define double @fms64(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fms64:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmsub d0, d0, d1, d2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
entry:
%mul = fmul double %b, -1.000000e+00
%0 = tail call double @llvm.fma.f64(double %a, double %mul, double %c)
ret double %0
}
ARM64: add more patterns for commuted fmsub operations. llvm-svn: 205206
2014-03-31 17:46:34 +02:00
define double @fms64_com(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fms64_com:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fmsub d0, d1, d0, d2
ARM64: add more patterns for commuted fmsub operations. llvm-svn: 205206
2014-03-31 17:46:34 +02:00
entry:
%mul = fmul double %b, -1.000000e+00
%0 = tail call double @llvm.fma.f64(double %mul, double %a, double %c)
ret double %0
}
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
define double @fnms64(double %a, double %b, double %c) nounwind readnone ssp {
; CHECK-LABEL: fnms64:
ARM64: fix fmsub patterns which assumed accum operand was first Confusingly, the NEON fmla instructions put the accumulator first but the scalar versions put it at the end (like the fma lib function & LLVM's intrinsic). This should fix PR19345, assuming there's only one issue. llvm-svn: 205758
2014-04-08 14:23:51 +02:00
; CHECK: fnmsub d0, d0, d1, d2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
entry:
%mul = fmul double %c, -1.000000e+00
%0 = tail call double @llvm.fma.f64(double %a, double %b, double %mul)
ret double %0
}
declare float @llvm.fma.f32(float, float, float) nounwind readnone
declare double @llvm.fma.f64(double, double, double) nounwind readnone
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