llvm-mirror/test/CodeGen/X86/v-binop-widen.ll

; RUN: llc -mcpu=generic -march=x86 -mattr=+sse < %s | FileCheck %s
; CHECK: divss
; CHECK: divps
; CHECK: divps

%vec = type <9 x float>
define %vec @vecdiv( %vec %p1, %vec %p2)
{
  %result = fdiv %vec %p1, %p2
  ret %vec %result
}
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558 2012-02-02 00:20:51 +01:00			`; RUN: llc -mcpu=generic -march=x86 -mattr=+sse < %s \| FileCheck %s`
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823 2013-06-25 04:48:58 +02:00			`; CHECK: divss`
Move v-binop-widen tests to X86 since they don't work on all platforms llvm-svn: 106562 2010-06-22 21:40:50 +02:00			`; CHECK: divps`
Change the x86 32-bit scheduler to register pressure and fix up the corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. llvm-svn: 127441 2011-03-11 02:05:58 +01:00			`; CHECK: divps`
Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen! llvm-svn: 106038 2010-06-15 22:29:05 +02:00
			`%vec = type <9 x float>`
			`define %vec @vecdiv( %vec %p1, %vec %p2)`
			`{`
			`%result = fdiv %vec %p1, %p2`
			`ret %vec %result`
			`}`
Revert "Temporarily enable MI-Sched on X86." This reverts commit 98a9b72e8c56dc13a2617de84503a3d78352789c. llvm-svn: 184823 2013-06-25 04:48:58 +02:00