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llvm-mirror/test/MC/RISCV/rv64zbr-valid.s

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[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With B extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-b -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-b < %s \
# RUN: | llvm-objdump --mattr=+experimental-b -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# With Bitmanip CRC extension:
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbr < %s \
# RUN: | llvm-objdump --mattr=+experimental-zbr -d -r - \
[RISCV] Fix unused check prefixes in test/MC/RISCV/
2020-10-30 05:18:00 +01:00
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
[RISCV] Add B extension tests to make sure RV64 only instructions aren't accepted in RV32. Add tests to make sure common instructions are accepted in RV64 and not just RV32. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D95150
2021-01-22 22:30:12 +01:00
# CHECK-ASM-AND-OBJ: crc32.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x03,0x61]
crc32.b t0, t1
# CHECK-ASM-AND-OBJ: crc32.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x13,0x61]
crc32.h t0, t1
# CHECK-ASM-AND-OBJ: crc32.w t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x23,0x61]
crc32.w t0, t1
# CHECK-ASM-AND-OBJ: crc32c.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x83,0x61]
crc32c.b t0, t1
# CHECK-ASM-AND-OBJ: crc32c.h t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x93,0x61]
crc32c.h t0, t1
# CHECK-ASM-AND-OBJ: crc32c.w t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0xa3,0x61]
crc32c.w t0, t1
[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) This adds the instruction encoding and mnenomics for the proposed RISC-V Bit Manipulation extension (version 0.92). It is implemented with each category of instruction as its own target feature, with the 'b' extension feature enabling all options. Since this extension is not yet ratified, all target features are prefixed with 'experimental-' to note their status. Differential Revision: https://reviews.llvm.org/D65649
2020-04-09 18:51:10 +02:00
# CHECK-ASM-AND-OBJ: crc32.d t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x33,0x61]
crc32.d t0, t1
# CHECK-ASM-AND-OBJ: crc32c.d t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0xb3,0x61]
crc32c.d t0, t1
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