llvm-mirror/test/MC/Disassembler/X86/enhanced.txt

# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 |& FileCheck %s

# CHECK: [o:jne][w:	][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606
0x0f 0x85 0xf6 0xff 0xff 0xff
# CHECK: [o:movq][w:	][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8
0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00
# CHECK: [o:xorps][w:	][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0
0x0f 0x57 0xd1
# CHECK: [o:andps][w:	][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0
0x0f 0x54 0xd1
Added a testcase for the enhanced disassembly bug fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. llvm-svn: 126182 2011-02-22 03:19:18 +01:00			`# RUN: llvm-mc --edis %s -triple=x86_64-apple-darwin9 \|& FileCheck %s`

			`# CHECK: [o:jne][w: ][0-p:-][0-l:10=10] <br> 0:[RIP/111](pc)=18446744073709551606`
			`0x0f 0x85 0xf6 0xff 0xff 0xff`
Fixed a bug in the enhanced disassembler that caused it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. llvm-svn: 126302 2011-02-23 04:31:28 +01:00			`# CHECK: [o:movq][w: ][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8`
			`0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00`
Insert dummy ED table entries for pseudo-instructions. The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. llvm-svn: 141562 2011-10-10 20:30:16 +02:00			`# CHECK: [o:xorps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0`
			`0x0f 0x57 0xd1`
			`# CHECK: [o:andps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0`
			`0x0f 0x54 0xd1`