2013-07-30 02:50:39 +02:00
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//===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the PowerPC-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// PPCGenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ppcfastisel"
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#include "PPC.h"
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#include "PPCISelLowering.h"
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#include "PPCSubtarget.h"
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#include "PPCTargetMachine.h"
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#include "MCTargetDesc/PPCPredicates.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/GlobalAlias.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Operator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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namespace {
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typedef struct Address {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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union {
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unsigned Reg;
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int FI;
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} Base;
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int Offset;
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// Innocuous defaults for our address.
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Address()
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: BaseType(RegBase), Offset(0) {
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Base.Reg = 0;
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}
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} Address;
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class PPCFastISel : public FastISel {
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const TargetMachine &TM;
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const TargetInstrInfo &TII;
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const TargetLowering &TLI;
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const PPCSubtarget &PPCSubTarget;
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LLVMContext *Context;
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public:
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explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo)
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: FastISel(FuncInfo, LibInfo),
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TM(FuncInfo.MF->getTarget()),
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TII(*TM.getInstrInfo()),
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TLI(*TM.getTargetLowering()),
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PPCSubTarget(
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*((static_cast<const PPCTargetMachine *>(&TM))->getSubtargetImpl())
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),
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Context(&FuncInfo.Fn->getContext()) { }
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// Backend specific FastISel code.
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private:
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virtual bool TargetSelectInstruction(const Instruction *I);
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virtual unsigned TargetMaterializeConstant(const Constant *C);
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virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
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virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
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const LoadInst *LI);
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virtual bool FastLowerArguments();
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2013-08-26 00:33:42 +02:00
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virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
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// Instruction selection routines.
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private:
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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2013-08-26 21:42:51 +02:00
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bool SelectRet(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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2013-07-30 02:50:39 +02:00
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// Utility routines.
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private:
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2013-08-26 00:33:42 +02:00
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bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt, unsigned DestReg);
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bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
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unsigned DestReg, bool IsZExt);
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2013-07-30 02:50:39 +02:00
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unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned PPCMaterializeInt(const Constant *C, MVT VT);
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unsigned PPCMaterialize32BitInt(int64_t Imm,
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const TargetRegisterClass *RC);
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unsigned PPCMaterialize64BitInt(int64_t Imm,
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const TargetRegisterClass *RC);
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2013-08-26 21:42:51 +02:00
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// Call handling routines.
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private:
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CCAssignFn *usePPC32CCs(unsigned Flag);
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2013-07-30 02:50:39 +02:00
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private:
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#include "PPCGenFastISel.inc"
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};
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} // end anonymous namespace
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2013-08-26 21:42:51 +02:00
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#include "PPCGenCallingConv.inc"
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// Function whose sole purpose is to kill compiler warnings
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// stemming from unused functions included from PPCGenCallingConv.inc.
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CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
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if (Flag == 1)
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return CC_PPC32_SVR4;
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else if (Flag == 2)
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return CC_PPC32_SVR4_ByVal;
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else if (Flag == 3)
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return CC_PPC32_SVR4_VarArg;
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else
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return RetCC_PPC;
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}
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2013-08-26 00:33:42 +02:00
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static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
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switch (Pred) {
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// These are not representable with any single compare.
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case CmpInst::FCMP_FALSE:
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case CmpInst::FCMP_UEQ:
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case CmpInst::FCMP_UGT:
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case CmpInst::FCMP_UGE:
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case CmpInst::FCMP_ULT:
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case CmpInst::FCMP_ULE:
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case CmpInst::FCMP_UNE:
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case CmpInst::FCMP_TRUE:
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default:
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return Optional<PPC::Predicate>();
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case CmpInst::FCMP_OEQ:
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case CmpInst::ICMP_EQ:
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return PPC::PRED_EQ;
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case CmpInst::FCMP_OGT:
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case CmpInst::ICMP_UGT:
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case CmpInst::ICMP_SGT:
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return PPC::PRED_GT;
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case CmpInst::FCMP_OGE:
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case CmpInst::ICMP_UGE:
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case CmpInst::ICMP_SGE:
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return PPC::PRED_GE;
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case CmpInst::FCMP_OLT:
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case CmpInst::ICMP_ULT:
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case CmpInst::ICMP_SLT:
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return PPC::PRED_LT;
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case CmpInst::FCMP_OLE:
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case CmpInst::ICMP_ULE:
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case CmpInst::ICMP_SLE:
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return PPC::PRED_LE;
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case CmpInst::FCMP_ONE:
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case CmpInst::ICMP_NE:
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return PPC::PRED_NE;
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case CmpInst::FCMP_ORD:
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return PPC::PRED_NU;
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case CmpInst::FCMP_UNO:
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return PPC::PRED_UN;
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}
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}
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// Attempt to fast-select a branch instruction.
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bool PPCFastISel::SelectBranch(const Instruction *I) {
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const BranchInst *BI = cast<BranchInst>(I);
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MachineBasicBlock *BrBB = FuncInfo.MBB;
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MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
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MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
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// For now, just try the simplest case where it's fed by a compare.
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if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
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Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
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if (!OptPPCPred)
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return false;
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PPC::Predicate PPCPred = OptPPCPred.getValue();
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// Take advantage of fall-through opportunities.
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if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
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std::swap(TBB, FBB);
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PPCPred = PPC::InvertPredicate(PPCPred);
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}
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unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
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if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
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CondReg))
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return false;
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BuildMI(*BrBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCC))
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.addImm(PPCPred).addReg(CondReg).addMBB(TBB);
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FastEmitBranch(FBB, DL);
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FuncInfo.MBB->addSuccessor(TBB);
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return true;
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} else if (const ConstantInt *CI =
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dyn_cast<ConstantInt>(BI->getCondition())) {
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uint64_t Imm = CI->getZExtValue();
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MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
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FastEmitBranch(Target, DL);
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return true;
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}
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// FIXME: ARM looks for a case where the block containing the compare
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// has been split from the block containing the branch. If this happens,
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// there is a vreg available containing the result of the compare. I'm
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// not sure we can do much, as we've lost the predicate information with
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// the compare instruction -- we have a 4-bit CR but don't know which bit
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// to test here.
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return false;
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}
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// Attempt to emit a compare of the two source values. Signed and unsigned
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// comparisons are supported. Return false if we can't handle it.
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bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
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bool IsZExt, unsigned DestReg) {
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Type *Ty = SrcValue1->getType();
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EVT SrcEVT = TLI.getValueType(Ty, true);
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if (!SrcEVT.isSimple())
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return false;
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MVT SrcVT = SrcEVT.getSimpleVT();
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// See if operand 2 is an immediate encodeable in the compare.
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// FIXME: Operands are not in canonical order at -O0, so an immediate
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// operand in position 1 is a lost opportunity for now. We are
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// similar to ARM in this regard.
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long Imm = 0;
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bool UseImm = false;
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// Only 16-bit integer constants can be represented in compares for
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// PowerPC. Others will be materialized into a register.
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if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
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if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
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SrcVT == MVT::i8 || SrcVT == MVT::i1) {
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const APInt &CIVal = ConstInt->getValue();
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Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
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if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
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UseImm = true;
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}
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}
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unsigned CmpOpc;
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bool NeedsExt = false;
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switch (SrcVT.SimpleTy) {
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default: return false;
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case MVT::f32:
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CmpOpc = PPC::FCMPUS;
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break;
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case MVT::f64:
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CmpOpc = PPC::FCMPUD;
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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NeedsExt = true;
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// Intentional fall-through.
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case MVT::i32:
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if (!UseImm)
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CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
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else
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CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
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break;
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case MVT::i64:
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if (!UseImm)
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CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
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else
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CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
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break;
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}
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unsigned SrcReg1 = getRegForValue(SrcValue1);
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if (SrcReg1 == 0)
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return false;
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unsigned SrcReg2 = 0;
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if (!UseImm) {
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SrcReg2 = getRegForValue(SrcValue2);
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if (SrcReg2 == 0)
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return false;
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}
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if (NeedsExt) {
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unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
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if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
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return false;
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SrcReg1 = ExtReg;
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if (!UseImm) {
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unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
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if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
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return false;
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SrcReg2 = ExtReg;
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}
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}
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if (!UseImm)
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
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.addReg(SrcReg1).addReg(SrcReg2);
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else
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc), DestReg)
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.addReg(SrcReg1).addImm(Imm);
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return true;
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}
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2013-08-26 21:42:51 +02:00
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// Attempt to fast-select a return instruction.
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bool PPCFastISel::SelectRet(const Instruction *I) {
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if (!FuncInfo.CanLowerReturn)
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return false;
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const ReturnInst *Ret = cast<ReturnInst>(I);
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const Function &F = *I->getParent()->getParent();
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// Build a list of return value registers.
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SmallVector<unsigned, 4> RetRegs;
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CallingConv::ID CC = F.getCallingConv();
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if (Ret->getNumOperands() > 0) {
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SmallVector<ISD::OutputArg, 4> Outs;
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GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ValLocs;
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CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, *Context);
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CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
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const Value *RV = Ret->getOperand(0);
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|
|
|
|
|
// FIXME: Only one output register for now.
|
|
|
|
if (ValLocs.size() > 1)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Special case for returning a constant integer of any size.
|
|
|
|
// Materialize the constant as an i64 and copy it to the return
|
|
|
|
// register. This avoids an unnecessary extend or truncate.
|
|
|
|
if (isa<ConstantInt>(*RV)) {
|
|
|
|
const Constant *C = cast<Constant>(RV);
|
|
|
|
unsigned SrcReg = PPCMaterializeInt(C, MVT::i64);
|
|
|
|
unsigned RetReg = ValLocs[0].getLocReg();
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
|
|
|
|
RetReg).addReg(SrcReg);
|
|
|
|
RetRegs.push_back(RetReg);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
unsigned Reg = getRegForValue(RV);
|
|
|
|
|
|
|
|
if (Reg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i < ValLocs.size(); ++i) {
|
|
|
|
|
|
|
|
CCValAssign &VA = ValLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
RetRegs.push_back(VA.getLocReg());
|
|
|
|
unsigned SrcReg = Reg + VA.getValNo();
|
|
|
|
|
|
|
|
EVT RVEVT = TLI.getValueType(RV->getType());
|
|
|
|
if (!RVEVT.isSimple())
|
|
|
|
return false;
|
|
|
|
MVT RVVT = RVEVT.getSimpleVT();
|
|
|
|
MVT DestVT = VA.getLocVT();
|
|
|
|
|
|
|
|
if (RVVT != DestVT && RVVT != MVT::i8 &&
|
|
|
|
RVVT != MVT::i16 && RVVT != MVT::i32)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (RVVT != DestVT) {
|
|
|
|
switch (VA.getLocInfo()) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unknown loc info!");
|
|
|
|
case CCValAssign::Full:
|
|
|
|
llvm_unreachable("Full value assign but types don't match?");
|
|
|
|
case CCValAssign::AExt:
|
|
|
|
case CCValAssign::ZExt: {
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
(DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
|
|
|
|
unsigned TmpReg = createResultReg(RC);
|
|
|
|
if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
|
|
|
|
return false;
|
|
|
|
SrcReg = TmpReg;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case CCValAssign::SExt: {
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
(DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
|
|
|
|
unsigned TmpReg = createResultReg(RC);
|
|
|
|
if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
|
|
|
|
return false;
|
|
|
|
SrcReg = TmpReg;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(TargetOpcode::COPY), RetRegs[i])
|
|
|
|
.addReg(SrcReg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(PPC::BLR));
|
|
|
|
|
|
|
|
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
|
|
|
|
MIB.addReg(RetRegs[i], RegState::Implicit);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-08-26 00:33:42 +02:00
|
|
|
// Attempt to emit an integer extend of SrcReg into DestReg. Both
|
|
|
|
// signed and zero extensions are supported. Return false if we
|
2013-08-26 21:42:51 +02:00
|
|
|
// can't handle it.
|
2013-08-26 00:33:42 +02:00
|
|
|
bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
|
|
|
unsigned DestReg, bool IsZExt) {
|
2013-08-26 21:42:51 +02:00
|
|
|
if (DestVT != MVT::i32 && DestVT != MVT::i64)
|
|
|
|
return false;
|
|
|
|
if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Signed extensions use EXTSB, EXTSH, EXTSW.
|
|
|
|
if (!IsZExt) {
|
|
|
|
unsigned Opc;
|
|
|
|
if (SrcVT == MVT::i8)
|
|
|
|
Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
|
|
|
|
else if (SrcVT == MVT::i16)
|
|
|
|
Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
|
|
|
|
else {
|
|
|
|
assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
|
|
|
|
Opc = PPC::EXTSW_32_64;
|
|
|
|
}
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
|
|
|
|
.addReg(SrcReg);
|
|
|
|
|
|
|
|
// Unsigned 32-bit extensions use RLWINM.
|
|
|
|
} else if (DestVT == MVT::i32) {
|
|
|
|
unsigned MB;
|
|
|
|
if (SrcVT == MVT::i8)
|
|
|
|
MB = 24;
|
|
|
|
else {
|
|
|
|
assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
|
|
|
|
MB = 16;
|
|
|
|
}
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLWINM),
|
|
|
|
DestReg)
|
|
|
|
.addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
|
|
|
|
|
|
|
|
// Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
|
|
|
|
} else {
|
|
|
|
unsigned MB;
|
|
|
|
if (SrcVT == MVT::i8)
|
|
|
|
MB = 56;
|
|
|
|
else if (SrcVT == MVT::i16)
|
|
|
|
MB = 48;
|
|
|
|
else
|
|
|
|
MB = 32;
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(PPC::RLDICL_32_64), DestReg)
|
|
|
|
.addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
2013-08-26 00:33:42 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Attempt to fast-select an indirect branch instruction.
|
|
|
|
bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
|
|
|
|
unsigned AddrReg = getRegForValue(I->getOperand(0));
|
|
|
|
if (AddrReg == 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::MTCTR8))
|
|
|
|
.addReg(AddrReg);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::BCTR8));
|
|
|
|
|
|
|
|
const IndirectBrInst *IB = cast<IndirectBrInst>(I);
|
|
|
|
for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
|
|
|
|
FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-08-26 21:42:51 +02:00
|
|
|
// Attempt to fast-select an integer extend instruction.
|
|
|
|
bool PPCFastISel::SelectIntExt(const Instruction *I) {
|
|
|
|
Type *DestTy = I->getType();
|
|
|
|
Value *Src = I->getOperand(0);
|
|
|
|
Type *SrcTy = Src->getType();
|
|
|
|
|
|
|
|
bool IsZExt = isa<ZExtInst>(I);
|
|
|
|
unsigned SrcReg = getRegForValue(Src);
|
|
|
|
if (!SrcReg) return false;
|
|
|
|
|
|
|
|
EVT SrcEVT, DestEVT;
|
|
|
|
SrcEVT = TLI.getValueType(SrcTy, true);
|
|
|
|
DestEVT = TLI.getValueType(DestTy, true);
|
|
|
|
if (!SrcEVT.isSimple())
|
|
|
|
return false;
|
|
|
|
if (!DestEVT.isSimple())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MVT SrcVT = SrcEVT.getSimpleVT();
|
|
|
|
MVT DestVT = DestEVT.getSimpleVT();
|
|
|
|
|
|
|
|
// If we know the register class needed for the result of this
|
|
|
|
// instruction, use it. Otherwise pick the register class of the
|
|
|
|
// correct size that does not contain X0/R0, since we don't know
|
|
|
|
// whether downstream uses permit that assignment.
|
|
|
|
unsigned AssignedReg = FuncInfo.ValueMap[I];
|
|
|
|
const TargetRegisterClass *RC =
|
|
|
|
(AssignedReg ? MRI.getRegClass(AssignedReg) :
|
|
|
|
(DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
|
|
|
|
&PPC::GPRC_and_GPRC_NOR0RegClass));
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
|
|
|
|
if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
UpdateValueMap(I, ResultReg);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2013-07-30 02:50:39 +02:00
|
|
|
// Attempt to fast-select an instruction that wasn't handled by
|
2013-08-26 00:33:42 +02:00
|
|
|
// the table-generated machinery.
|
2013-07-30 02:50:39 +02:00
|
|
|
bool PPCFastISel::TargetSelectInstruction(const Instruction *I) {
|
2013-08-26 00:33:42 +02:00
|
|
|
|
|
|
|
switch (I->getOpcode()) {
|
|
|
|
case Instruction::Br:
|
|
|
|
return SelectBranch(I);
|
|
|
|
case Instruction::IndirectBr:
|
|
|
|
return SelectIndirectBr(I);
|
2013-08-26 21:42:51 +02:00
|
|
|
case Instruction::Ret:
|
|
|
|
return SelectRet(I);
|
|
|
|
case Instruction::ZExt:
|
|
|
|
case Instruction::SExt:
|
|
|
|
return SelectIntExt(I);
|
2013-08-26 00:33:42 +02:00
|
|
|
// Here add other flavors of Instruction::XXX that automated
|
|
|
|
// cases don't catch. For example, switches are terminators
|
|
|
|
// that aren't yet handled.
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return false;
|
2013-07-30 02:50:39 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
// Materialize a floating-point constant into a register, and return
|
|
|
|
// the register number (or zero if we failed to handle it).
|
|
|
|
unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
|
|
|
|
// No plans to handle long double here.
|
|
|
|
if (VT != MVT::f32 && VT != MVT::f64)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
// All FP constants are loaded from the constant pool.
|
|
|
|
unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
|
|
|
|
assert(Align > 0 && "Unexpectedly missing alignment information!");
|
|
|
|
unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
|
|
|
|
unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
|
|
|
|
CodeModel::Model CModel = TM.getCodeModel();
|
|
|
|
|
|
|
|
MachineMemOperand *MMO =
|
|
|
|
FuncInfo.MF->getMachineMemOperand(
|
|
|
|
MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
|
|
|
|
(VT == MVT::f32) ? 4 : 8, Align);
|
|
|
|
|
2013-08-26 00:33:42 +02:00
|
|
|
unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
|
|
|
|
unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
|
|
|
|
|
|
|
|
// For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
|
|
|
|
if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
|
2013-07-30 02:50:39 +02:00
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::LDtocCPT),
|
2013-08-26 00:33:42 +02:00
|
|
|
TmpReg)
|
|
|
|
.addConstantPoolIndex(Idx).addReg(PPC::X2);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
|
|
|
|
.addImm(0).addReg(TmpReg).addMemOperand(MMO);
|
|
|
|
} else {
|
2013-07-30 02:50:39 +02:00
|
|
|
// Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ADDIStocHA),
|
|
|
|
TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
|
|
|
|
.addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
|
|
|
|
.addReg(TmpReg)
|
|
|
|
.addMemOperand(MMO);
|
|
|
|
}
|
|
|
|
|
|
|
|
return DestReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Materialize a 32-bit integer constant into a register, and return
|
|
|
|
// the register number (or zero if we failed to handle it).
|
|
|
|
unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
|
|
|
|
const TargetRegisterClass *RC) {
|
|
|
|
unsigned Lo = Imm & 0xFFFF;
|
|
|
|
unsigned Hi = (Imm >> 16) & 0xFFFF;
|
|
|
|
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
|
|
|
|
|
|
|
|
if (isInt<16>(Imm))
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
|
|
|
|
.addImm(Imm);
|
|
|
|
else if (Lo) {
|
|
|
|
// Both Lo and Hi have nonzero bits.
|
|
|
|
unsigned TmpReg = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
|
|
|
|
.addImm(Hi);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
|
|
|
|
.addReg(TmpReg).addImm(Lo);
|
|
|
|
} else
|
|
|
|
// Just Hi bits.
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
|
|
TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
|
|
|
|
.addImm(Hi);
|
|
|
|
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Materialize a 64-bit integer constant into a register, and return
|
|
|
|
// the register number (or zero if we failed to handle it).
|
|
|
|
unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
|
|
|
|
const TargetRegisterClass *RC) {
|
|
|
|
unsigned Remainder = 0;
|
|
|
|
unsigned Shift = 0;
|
|
|
|
|
|
|
|
// If the value doesn't fit in 32 bits, see if we can shift it
|
|
|
|
// so that it fits in 32 bits.
|
|
|
|
if (!isInt<32>(Imm)) {
|
|
|
|
Shift = countTrailingZeros<uint64_t>(Imm);
|
|
|
|
int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
|
|
|
|
|
|
|
|
if (isInt<32>(ImmSh))
|
|
|
|
Imm = ImmSh;
|
|
|
|
else {
|
|
|
|
Remainder = Imm;
|
|
|
|
Shift = 32;
|
|
|
|
Imm >>= 32;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Handle the high-order 32 bits (if shifted) or the whole 32 bits
|
|
|
|
// (if not shifted).
|
|
|
|
unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
|
|
|
|
if (!Shift)
|
|
|
|
return TmpReg1;
|
|
|
|
|
|
|
|
// If upper 32 bits were not zero, we've built them and need to shift
|
|
|
|
// them into place.
|
|
|
|
unsigned TmpReg2;
|
|
|
|
if (Imm) {
|
|
|
|
TmpReg2 = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::RLDICR),
|
|
|
|
TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
|
|
|
|
} else
|
|
|
|
TmpReg2 = TmpReg1;
|
|
|
|
|
|
|
|
unsigned TmpReg3, Hi, Lo;
|
|
|
|
if ((Hi = (Remainder >> 16) & 0xFFFF)) {
|
|
|
|
TmpReg3 = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORIS8),
|
|
|
|
TmpReg3).addReg(TmpReg2).addImm(Hi);
|
|
|
|
} else
|
|
|
|
TmpReg3 = TmpReg2;
|
|
|
|
|
|
|
|
if ((Lo = Remainder & 0xFFFF)) {
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(PPC::ORI8),
|
|
|
|
ResultReg).addReg(TmpReg3).addImm(Lo);
|
|
|
|
return ResultReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
return TmpReg3;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
// Materialize an integer constant into a register, and return
|
|
|
|
// the register number (or zero if we failed to handle it).
|
|
|
|
unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT) {
|
|
|
|
|
|
|
|
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
|
|
|
|
VT != MVT::i8 && VT != MVT::i1)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
|
|
|
|
&PPC::GPRCRegClass);
|
|
|
|
|
|
|
|
// If the constant is in range, use a load-immediate.
|
|
|
|
const ConstantInt *CI = cast<ConstantInt>(C);
|
|
|
|
if (isInt<16>(CI->getSExtValue())) {
|
|
|
|
unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
|
|
|
|
unsigned ImmReg = createResultReg(RC);
|
|
|
|
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ImmReg)
|
|
|
|
.addImm(CI->getSExtValue());
|
|
|
|
return ImmReg;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Construct the constant piecewise.
|
|
|
|
int64_t Imm = CI->getZExtValue();
|
|
|
|
|
|
|
|
if (VT == MVT::i64)
|
|
|
|
return PPCMaterialize64BitInt(Imm, RC);
|
|
|
|
else if (VT == MVT::i32)
|
|
|
|
return PPCMaterialize32BitInt(Imm, RC);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Materialize a constant into a register, and return the register
|
|
|
|
// number (or zero if we failed to handle it).
|
|
|
|
unsigned PPCFastISel::TargetMaterializeConstant(const Constant *C) {
|
|
|
|
EVT CEVT = TLI.getValueType(C->getType(), true);
|
|
|
|
|
|
|
|
// Only handle simple types.
|
|
|
|
if (!CEVT.isSimple()) return 0;
|
|
|
|
MVT VT = CEVT.getSimpleVT();
|
|
|
|
|
|
|
|
if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
|
|
|
|
return PPCMaterializeFP(CFP, VT);
|
|
|
|
else if (isa<ConstantInt>(C))
|
|
|
|
return PPCMaterializeInt(C, VT);
|
|
|
|
// TBD: Global values.
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Materialize the address created by an alloca into a register, and
|
|
|
|
// return the register number (or zero if we failed to handle it). TBD.
|
|
|
|
unsigned PPCFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
|
|
|
|
return AI && 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Fold loads into extends when possible. TBD.
|
|
|
|
bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
|
|
|
|
const LoadInst *LI) {
|
|
|
|
return MI && OpNo && LI && false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Attempt to lower call arguments in a faster way than done by
|
|
|
|
// the selection DAG code.
|
|
|
|
bool PPCFastISel::FastLowerArguments() {
|
|
|
|
// Defer to normal argument lowering for now. It's reasonably
|
|
|
|
// efficient. Consider doing something like ARM to handle the
|
|
|
|
// case where all args fit in registers, no varargs, no float
|
|
|
|
// or vector args.
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2013-08-26 00:33:42 +02:00
|
|
|
// Handle materializing integer constants into a register. This is not
|
|
|
|
// automatically generated for PowerPC, so must be explicitly created here.
|
|
|
|
unsigned PPCFastISel::FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
|
|
|
|
|
|
|
|
if (Opc != ISD::Constant)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
|
|
|
|
VT != MVT::i8 && VT != MVT::i1)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
|
|
|
|
&PPC::GPRCRegClass);
|
|
|
|
if (VT == MVT::i64)
|
|
|
|
return PPCMaterialize64BitInt(Imm, RC);
|
|
|
|
else
|
|
|
|
return PPCMaterialize32BitInt(Imm, RC);
|
|
|
|
}
|
|
|
|
|
2013-07-30 02:50:39 +02:00
|
|
|
namespace llvm {
|
|
|
|
// Create the fast instruction selector for PowerPC64 ELF.
|
|
|
|
FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
|
|
|
|
const TargetLibraryInfo *LibInfo) {
|
|
|
|
const TargetMachine &TM = FuncInfo.MF->getTarget();
|
|
|
|
|
|
|
|
// Only available on 64-bit ELF for now.
|
|
|
|
const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
|
|
|
|
if (Subtarget->isPPC64() && Subtarget->isSVR4ABI())
|
|
|
|
return new PPCFastISel(FuncInfo, LibInfo);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|