2014-11-07 15:24:31 +01:00
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//===---- MipsCCState.h - CCState with Mips specific extensions -----------===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2014-11-07 15:24:31 +01:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSCCSTATE_H
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#define MIPSCCSTATE_H
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2015-01-14 12:23:27 +01:00
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#include "MipsISelLowering.h"
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2014-11-07 15:24:31 +01:00
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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namespace llvm {
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class SDNode;
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class MipsSubtarget;
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class MipsCCState : public CCState {
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public:
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enum SpecialCallingConvType { Mips16RetHelperConv, NoSpecialCallingConv };
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/// Determine the SpecialCallingConvType for the given callee
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static SpecialCallingConvType
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getSpecialCallingConvForCallee(const SDNode *Callee,
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const MipsSubtarget &Subtarget);
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private:
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/// Identify lowered values that originated from f128 arguments and record
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/// this for use by RetCC_MipsN.
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void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins,
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2017-04-26 13:10:38 +02:00
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const Type *RetTy, const char * Func);
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2014-11-07 15:24:31 +01:00
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/// Identify lowered values that originated from f128 arguments and record
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/// this for use by RetCC_MipsN.
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void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
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/// Identify lowered values that originated from f128 arguments and record
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/// this.
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void
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PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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std::vector<TargetLowering::ArgListEntry> &FuncArgs,
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2017-04-26 13:10:38 +02:00
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const char *Func);
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2014-11-07 15:24:31 +01:00
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/// Identify lowered values that originated from f128 arguments and record
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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/// this for use by RetCC_MipsN.
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2014-11-07 15:24:31 +01:00
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void
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PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins);
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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void
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PreAnalyzeCallResultForVectorFloat(const SmallVectorImpl<ISD::InputArg> &Ins,
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const Type *RetTy);
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void PreAnalyzeFormalArgumentsForVectorFloat(
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const SmallVectorImpl<ISD::InputArg> &Ins);
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void
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PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
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2014-11-07 15:24:31 +01:00
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/// Records whether the value has been lowered from an f128.
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SmallVector<bool, 4> OriginalArgWasF128;
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2014-11-07 17:54:21 +01:00
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/// Records whether the value has been lowered from float.
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SmallVector<bool, 4> OriginalArgWasFloat;
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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/// Records whether the value has been lowered from a floating point vector.
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SmallVector<bool, 4> OriginalArgWasFloatVector;
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/// Records whether the return value has been lowered from a floating point
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/// vector.
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SmallVector<bool, 4> OriginalRetWasFloatVector;
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2014-11-07 15:24:31 +01:00
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/// Records whether the value was a fixed argument.
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/// See ISD::OutputArg::IsFixed,
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SmallVector<bool, 4> CallOperandIsFixed;
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// Used to handle MIPS16-specific calling convention tweaks.
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// FIXME: This should probably be a fully fledged calling convention.
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SpecialCallingConvType SpecialCallingConv;
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public:
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MipsCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
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SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
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SpecialCallingConvType SpecialCC = NoSpecialCallingConv)
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: CCState(CC, isVarArg, MF, locs, C), SpecialCallingConv(SpecialCC) {}
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void
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AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn,
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std::vector<TargetLowering::ArgListEntry> &FuncArgs,
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2017-04-26 13:10:38 +02:00
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const char *Func) {
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PreAnalyzeCallOperands(Outs, FuncArgs, Func);
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2014-11-07 15:24:31 +01:00
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CCState::AnalyzeCallOperands(Outs, Fn);
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OriginalArgWasF128.clear();
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2014-11-07 17:54:21 +01:00
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OriginalArgWasFloat.clear();
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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OriginalArgWasFloatVector.clear();
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2014-11-07 15:24:31 +01:00
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CallOperandIsFixed.clear();
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}
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// The AnalyzeCallOperands in the base class is not usable since we must
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// provide a means of accessing ArgListEntry::IsFixed. Delete them from this
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// class. This doesn't stop them being used via the base class though.
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void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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2015-02-15 23:54:22 +01:00
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CCAssignFn Fn) = delete;
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2014-11-07 15:24:31 +01:00
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void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs,
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SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
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2015-02-15 23:54:22 +01:00
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CCAssignFn Fn) = delete;
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2014-11-07 15:24:31 +01:00
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void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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CCAssignFn Fn) {
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PreAnalyzeFormalArgumentsForF128(Ins);
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CCState::AnalyzeFormalArguments(Ins, Fn);
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2014-11-07 17:54:21 +01:00
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OriginalArgWasFloat.clear();
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2014-11-07 15:24:31 +01:00
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OriginalArgWasF128.clear();
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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OriginalArgWasFloatVector.clear();
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2014-11-07 15:24:31 +01:00
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}
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void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
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2017-04-26 13:10:38 +02:00
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CCAssignFn Fn, const Type *RetTy,
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const char *Func) {
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PreAnalyzeCallResultForF128(Ins, RetTy, Func);
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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PreAnalyzeCallResultForVectorFloat(Ins, RetTy);
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2014-11-07 15:24:31 +01:00
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CCState::AnalyzeCallResult(Ins, Fn);
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2014-11-07 17:54:21 +01:00
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OriginalArgWasFloat.clear();
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2014-11-07 15:24:31 +01:00
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OriginalArgWasF128.clear();
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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OriginalArgWasFloatVector.clear();
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2014-11-07 15:24:31 +01:00
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}
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void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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CCAssignFn Fn) {
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PreAnalyzeReturnForF128(Outs);
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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PreAnalyzeReturnForVectorFloat(Outs);
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2014-11-07 15:24:31 +01:00
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CCState::AnalyzeReturn(Outs, Fn);
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2014-11-07 17:54:21 +01:00
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OriginalArgWasFloat.clear();
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2014-11-07 15:24:31 +01:00
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OriginalArgWasF128.clear();
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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OriginalArgWasFloatVector.clear();
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2014-11-07 15:24:31 +01:00
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}
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bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
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CCAssignFn Fn) {
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PreAnalyzeReturnForF128(ArgsFlags);
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
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PreAnalyzeReturnForVectorFloat(ArgsFlags);
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2014-11-07 15:24:31 +01:00
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bool Return = CCState::CheckReturn(ArgsFlags, Fn);
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2014-11-07 17:54:21 +01:00
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OriginalArgWasFloat.clear();
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2014-11-07 15:24:31 +01:00
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OriginalArgWasF128.clear();
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Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
|
|
|
OriginalArgWasFloatVector.clear();
|
2014-11-07 15:24:31 +01:00
|
|
|
return Return;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; }
|
2014-11-07 17:54:21 +01:00
|
|
|
bool WasOriginalArgFloat(unsigned ValNo) {
|
|
|
|
return OriginalArgWasFloat[ValNo];
|
|
|
|
}
|
Reland "[SelectionDAG] Enable target specific vector scalarization of calls and returns"
By target hookifying getRegisterType, getNumRegisters, getVectorBreakdown,
backends can request that LLVM to scalarize vector types for calls
and returns.
The MIPS vector ABI requires that vector arguments and returns are passed in
integer registers. With SelectionDAG's new hooks, the MIPS backend can now
handle LLVM-IR with vector types in calls and returns. E.g.
'call @foo(<4 x i32> %4)'.
Previously these cases would be scalarized for the MIPS O32/N32/N64 ABI for
calls and returns if vector types were not legal. If vector types were legal,
a single 128bit vector argument would be assigned to a single 32 bit / 64 bit
integer register.
By teaching the MIPS backend to inspect the original types, it can now
implement the MIPS vector ABI which requires a particular method of
scalarizing vectors.
Previously, the MIPS backend relied on clang to scalarize types such as "call
@foo(<4 x float> %a) into "call @foo(i32 inreg %1, i32 inreg %2, i32 inreg %3,
i32 inreg %4)".
This patch enables the MIPS backend to take either form for vector types.
The previous version of this patch had a "conditional move or jump depends on
uninitialized value".
Reviewers: zoran.jovanovic, jaydeep, vkalintiris, slthakur
Differential Revision: https://reviews.llvm.org/D27845
llvm-svn: 305083
2017-06-09 16:37:08 +02:00
|
|
|
bool WasOriginalArgVectorFloat(unsigned ValNo) const {
|
|
|
|
return OriginalArgWasFloatVector[ValNo];
|
|
|
|
}
|
|
|
|
bool WasOriginalRetVectorFloat(unsigned ValNo) const {
|
|
|
|
return OriginalRetWasFloatVector[ValNo];
|
|
|
|
}
|
2014-11-07 15:24:31 +01:00
|
|
|
bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; }
|
|
|
|
SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; }
|
|
|
|
};
|
2015-06-23 11:49:53 +02:00
|
|
|
}
|
2014-11-07 15:24:31 +01:00
|
|
|
|
|
|
|
#endif
|