RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-24 21:42:54 +02:00
Code Issues Projects Releases Wiki Activity
798b42868c
llvm-mirror/test/CodeGen/X86/i8-umulo.ll

25 lines
619 B
LLVM
Raw Normal View History

[X86] Fix checked arithmetic for i8 on X86. When lowering a ISD::BRCOND into a test+branch, make sure that we always use the correct condition code to emit the test operation. This fixes PR19858: "i8 checked mul is wrong on x86". Patch by Keno Fisher! llvm-svn: 210032
2014-06-02 18:00:27 +02:00
; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
; PR19858
declare {i8, i1} @llvm.umul.with.overflow.i8(i8 %a, i8 %b)
define i8 @testumulo(i32 %argc) {
[SDAG] Introduce a combined set to the DAG combiner which tracks nodes which have successfully round-tripped through the combine phase, and use this to ensure all operands to DAG nodes are visited by the combiner, even if they are only added during the combine phase. This is critical to have the combiner reach nodes that are *introduced* during combining. Previously these would sometimes be visited and sometimes not be visited based on whether they happened to end up on the worklist or not. Now we always run them through the combiner. This fixes quite a few bad codegen test cases lurking in the suite while also being more principled. Among these, the TLS codegeneration is particularly exciting for programs that have this in the critical path like TSan-instrumented binaries (although I think they engineer to use a different TLS that is faster anyways). I've tried to check for compile-time regressions here by running llc over a merged (but not LTO-ed) clang bitcode file and observed at most a 3% slowdown in llc. Given that this is essentially a worst case (none of opt or clang are running at this phase) I think this is tolerable. The actual LTO case should be even less costly, and the cost in normal compilation should be negligible. With this combining logic, it is possible to re-legalize as we combine which is necessary to implement PSHUFB formation on x86 as a post-legalize DAG combine (my ultimate goal). Differential Revision: http://reviews.llvm.org/D4638 llvm-svn: 213898
2014-07-25 00:15:28 +02:00
; CHECK: imull
[X86] Fix checked arithmetic for i8 on X86. When lowering a ISD::BRCOND into a test+branch, make sure that we always use the correct condition code to emit the test operation. This fixes PR19858: "i8 checked mul is wrong on x86". Patch by Keno Fisher! llvm-svn: 210032
2014-06-02 18:00:27 +02:00
; CHECK: testb %{{.+}}, %{{.+}}
; CHECK: je [[NOOVERFLOWLABEL:.+]]
; CHECK: {{.*}}[[NOOVERFLOWLABEL]]:
; CHECK-NEXT: movb
; CHECK-NEXT: retl
top:
%RHS = trunc i32 %argc to i8
%umul = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 25, i8 %RHS)
%ex = extractvalue { i8, i1 } %umul, 1
br i1 %ex, label %overflow, label %nooverlow
overflow:
ret i8 %RHS
nooverlow:
%umul.value = extractvalue { i8, i1 } %umul, 0
ret i8 %umul.value
}
Reference in New Issue Copy Permalink