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llvm-mirror/test/CodeGen/X86/add-of-carry.ll

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When adding the carry bit to another value on X86, exploit the fact that the carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
2010-09-21 20:41:19 +02:00
; RUN: llc < %s -march=x86 | FileCheck %s
; <rdar://problem/8449754>
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-19 23:08:31 +01:00
define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
2010-09-21 20:41:19 +02:00
entry:
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-19 23:08:31 +01:00
; CHECK: test1:
When adding the carry bit to another value on X86, exploit the fact that the carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
2010-09-21 20:41:19 +02:00
; CHECK: sbbl %ecx, %ecx
; CHECK-NOT: addl
; CHECK: subl %ecx, %eax
%add4 = add i32 %x, %sum
%cmp = icmp ult i32 %add4, %x
%inc = zext i1 %cmp to i32
%z.0 = add i32 %add4, %inc
ret i32 %z.0
}
improve the setcc -> setcc_carry optimization to happen more consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
2010-12-19 23:08:31 +01:00
; Instcombine transforms test1 into test2:
; CHECK: test2:
; CHECK: movl
; CHECK-NEXT: addl
; CHECK-NEXT: sbbl
; CHECK-NEXT: subl
; CHECK-NEXT: ret
define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp {
entry:
%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %sum)
%0 = extractvalue { i32, i1 } %uadd, 0
%cmp = extractvalue { i32, i1 } %uadd, 1
%inc = zext i1 %cmp to i32
%z.0 = add i32 %0, %inc
ret i32 %z.0
}
declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
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