2004-09-07 00:58:13 +02:00
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<title>Writing an LLVM backend</title>
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<link rel="stylesheet" href="llvm.css" type="text/css">
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</head>
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<body>
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<div class="doc_title">
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Writing an LLVM backend
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</div>
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<ol>
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<li><a href="#intro">Introduction</a>
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<li><a href="#backends">Writing a backend</a>
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<ol>
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2004-09-18 08:28:07 +02:00
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<li><a href="#machine">Machine backends</a>
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2004-09-07 00:58:13 +02:00
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<ol>
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<li><a href="#machineTOC">Outline</a></li>
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<li><a href="#machineDetails">Implementation details</a></li>
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</ol></li>
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<li><a href="#machine">Machine backends</a></li>
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<li><a href="#lang">Language backends</a></li>
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</ol></li>
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<li><a href="#related">Related reading material</a>
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</ol>
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<div class="doc_author">
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<p>Written by <a href="http://misha.brukman.net">Misha Brukman</a></p>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="intro">Introduction</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<p>This document describes techniques for writing backends for LLVM which
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convert the LLVM representation to machine assembly code or other languages.</p>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="backends">Writing a backend</a>
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</div>
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<!-- *********************************************************************** -->
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="machine">Machine backends</a>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="machineTOC">Outline</a>
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</div>
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<div class="doc_text">
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<p>In general, you want to follow the format of X86 or PowerPC (in
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<tt>lib/Target</tt>).</p>
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<p>To create a static compiler (one that emits text assembly), you need to
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implement the following:</p>
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<ul>
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<li>Describe the register set
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<ul>
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<li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
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the register set and register classes</li>
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<li>Implement a subclass of <tt><a
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href="CodeGenerator.html#mregisterinfo">MRegisterInfo</a></tt></li>
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</ul></li>
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<li>Describe the instruction set
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<ul>
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<li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
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the instruction set</li>
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<li>Implement a subclass of <tt><a
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href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></tt></li>
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</ul></li>
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<li>Describe the target machine
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<ul>
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<li>Create a <a href="TableGenFundamentals.html">TableGen</a> description of
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the target that describes the pointer size and references the instruction
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set</li>
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<li>Implement a subclass of <tt><a
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href="CodeGenerator.html#targetmachine">TargetMachine</a></tt>, which
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configures <tt><a href="CodeGenerator.html#targetdata">TargetData</a></tt>
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correctly</li>
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</ul></li>
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<li>Implement the assembly printer for the architecture. Usually, if you have
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described the instruction set with the assembly printer generator in mind, that
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step can be almost automated.</li>
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</ul>
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<p>Now, for static code generation you also need to write an instruction
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selector for your platform: see <tt>lib/Target/*/*ISelSimple.cpp</tt> which
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is no longer "simple" but it gives you the idea: you have to be able to create
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MachineInstrs for any given LLVM instruction using the <tt>InstVisitor</tt>
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pattern, and produce a <tt>MachineFunction</tt> with
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<tt>MachineBasicBlock</tt>s full of <tt><a
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href="CodeGenerator.html#machineinstr">MachineInstr</a></tt>s for a
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corresponding LLVM Function. Creating an instruction selector is perhaps the
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most time-consuming part of creating a back-end.</p>
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<p>To create a JIT for your platform:</p>
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<ul>
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<li>Create a subclass of <tt><a
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href="CodeGenerator.html#targetjitinfo">TargetJITInfo</a></tt></li>
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<li>Create a machine code emitter that will be used to emit binary code
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directly into memory, given <tt>MachineInstr</tt>s</li>
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</ul>
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<p>Note that <tt>lib/target/Skeleton</tt> is a clean skeleton for a new target,
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so you might want to start with that and adapt it for your target, and if you
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are wondering how things are done, peek in the X86 or PowerPC target.</p>
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<p>The Skeleton target is non-functional but provides the basic building blocks
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you will need for your endeavor.</p>
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</div>
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<!-- _______________________________________________________________________ -->
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<div class="doc_subsubsection">
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<a name="machineDetails">Implementation details</a>
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</div>
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<div class="doc_text">
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<ul>
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<li><p><b>TableGen register info description</b> - describe a class which
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will store the register's number in the binary encoding of the instruction
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(e.g., for JIT purposes).</p>
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<p>You also need to define register classes to contain these registers, such as
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the integer register class and floating-point register class, so that you can
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allocate virtual registers to instructions from these sets, and let the
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target-independent register allocator automatically choose the actual
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architected registers.</p>
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<div class="doc_code">
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<pre>
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// class Register is defined in Target.td
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<b>class</b> <em>Target</em>Reg<string name> : Register<name> {
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<b>let</b> Namespace = "<em>Target</em>";
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}
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2004-09-18 08:28:07 +02:00
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<b>class</b> IntReg<<b>bits</b><5> num, string name> : <em>Target</em>Reg<name> {
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<b>field</b> <b>bits</b><5> Num = num;
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}
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<b>def</b> R0 : IntReg<0, "%R0">;
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...
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// class RegisterClass is defined in Target.td
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<b>def</b> IReg : RegisterClass<i64, 64, [R0, ... ]>;
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</pre>
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</div>
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</li>
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<li><p><b>TableGen instruction info description</b> - break up instructions into
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classes, usually that's already done by the manufacturer (see instruction
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manual). Define a class for each instruction category. Define each opcode as a
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subclass of the category, with appropriate parameters such as the fixed binary
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encoding of opcodes and extended opcodes, and map the register bits to the bits
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of the instruction which they are encoded in (for the JIT). Also specify how
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the instruction should be printed so it can use the automatic assembly printer,
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e.g.:</p>
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<div class="doc_code">
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<pre>
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// class Instruction is defined in Target.td
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<b>class</b> Form<<b>bits</b><6> opcode, <b>dag</b> OL, <b>string</b> asmstr> : Instruction {
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<b>field</b> <b>bits</b><42> Inst;
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<b>let</b> Namespace = "<em>Target</em>";
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<b>let</b> Inst{0-6} = opcode;
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<b>let</b> OperandList = OL;
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<b>let</b> AsmString = asmstr;
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}
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<b>def</b> ADD : Form<42, (ops IReg:$rD, IReg:$rA, IReg:$rB), "add $rD, $rA, $rB">;
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</pre>
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</div>
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</li>
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</ul>
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</div>
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<!-- ======================================================================= -->
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<div class="doc_subsection">
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<a name="lang">Language backends</a>
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</div>
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<div class="doc_text">
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<p>For now, just take a look at <tt>lib/Target/CBackend</tt> for an example of
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how the C backend is written.</p>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_section">
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<a name="related">Related reading material</a>
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</div>
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<!-- *********************************************************************** -->
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<div class="doc_text">
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<ul>
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<li><a href="CodeGenerator.html">Code generator</a> -
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describes some of the classes in code generation at a high level, but
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it is not (yet) complete.</li>
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<li><a href="TableGenFundamentals.html">TableGen fundamentals</a> -
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describes how to use TableGen to describe your target information succinctly
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</li>
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</ul>
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</div>
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<!-- *********************************************************************** -->
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<a href="http://misha.brukman.net">Misha Brukman</a><br>
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<a href="http://llvm.cs.uiuc.edu">The LLVM Compiler Infrastructure</a>
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<br>
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Last modified: $Date$
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</address>
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</body>
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</html>
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