2005-10-16 07:39:50 +02:00
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//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===//
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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2004-08-17 06:55:41 +02:00
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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2005-10-15 01:51:18 +02:00
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#include "PPC.h"
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2005-10-15 01:45:43 +02:00
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#include "PPCInstrBuilder.h"
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2006-11-16 23:43:37 +01:00
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#include "PPCMachineFunctionInfo.h"
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2005-10-15 01:59:06 +02:00
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#include "PPCRegisterInfo.h"
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2006-11-16 23:43:37 +01:00
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#include "PPCFrameInfo.h"
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2006-07-11 02:48:23 +02:00
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#include "PPCSubtarget.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/Constants.h"
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2008-04-02 02:25:04 +02:00
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#include "llvm/Function.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-01-26 22:22:28 +01:00
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#include "llvm/CodeGen/MachineModuleInfo.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2006-03-23 19:12:57 +01:00
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#include "llvm/CodeGen/MachineLocation.h"
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2007-12-31 05:13:23 +01:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2008-03-03 23:19:16 +01:00
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#include "llvm/CodeGen/RegisterScavenging.h"
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2006-04-07 18:34:46 +02:00
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/Target/TargetFrameInfo.h"
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2006-04-17 23:48:13 +02:00
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#include "llvm/Target/TargetInstrInfo.h"
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2004-08-17 06:55:41 +02:00
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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2004-09-02 00:55:40 +02:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2005-11-06 10:00:38 +01:00
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#include "llvm/Support/MathExtras.h"
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2007-02-19 22:49:54 +01:00
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#include "llvm/ADT/BitVector.h"
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2004-09-02 00:55:40 +02:00
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#include "llvm/ADT/STLExtras.h"
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2004-08-17 06:55:41 +02:00
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#include <cstdlib>
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using namespace llvm;
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2008-03-10 23:59:46 +01:00
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// FIXME This disables some code that aligns the stack to a boundary
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// bigger than the default (16 bytes on Darwin) when there is a stack local
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// of greater alignment. This does not currently work, because the delta
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// between old and new stack pointers is added to offsets that reference
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// incoming parameters after the prolog is generated, and the code that
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// does that doesn't handle a variable delta. You don't want to do that
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// anyway; a better approach is to reserve another register that retains
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// to the incoming stack pointer, and reference parameters relative to that.
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#define ALIGN_STACK 0
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2008-03-05 00:13:51 +01:00
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// FIXME (64-bit): Eventually enable by default.
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2008-03-10 23:49:16 +01:00
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cl::opt<bool> EnablePPC32RS("enable-ppc32-regscavenger",
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cl::init(false),
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cl::desc("Enable PPC32 register scavenger"),
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cl::Hidden);
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cl::opt<bool> EnablePPC64RS("enable-ppc64-regscavenger",
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cl::init(false),
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cl::desc("Enable PPC64 register scavenger"),
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cl::Hidden);
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#define EnableRegisterScavenging \
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((EnablePPC32RS && !Subtarget.isPPC64()) || \
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(EnablePPC64RS && Subtarget.isPPC64()))
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2008-03-05 00:13:51 +01:00
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2008-03-03 23:19:16 +01:00
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// FIXME (64-bit): Should be inlined.
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bool
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PPCRegisterInfo::requiresRegisterScavenging(const MachineFunction &) const {
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2008-03-10 23:49:16 +01:00
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return EnableRegisterScavenging;
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2008-03-03 23:19:16 +01:00
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}
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2006-04-17 23:07:20 +02:00
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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2006-07-11 22:53:55 +02:00
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using namespace PPC;
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2006-04-17 23:07:20 +02:00
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switch (RegEnum) {
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2008-02-13 18:24:14 +01:00
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case 0: return 0;
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2008-03-10 15:12:10 +01:00
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case R0 : case X0 : case F0 : case V0 : case CR0: case CR0LT: return 0;
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case R1 : case X1 : case F1 : case V1 : case CR1: case CR0GT: return 1;
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case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
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case R3 : case X3 : case F3 : case V3 : case CR3: case CR0UN: return 3;
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case R4 : case X4 : case F4 : case V4 : case CR4: case CR1LT: return 4;
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case R5 : case X5 : case F5 : case V5 : case CR5: case CR1GT: return 5;
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case R6 : case X6 : case F6 : case V6 : case CR6: case CR1EQ: return 6;
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case R7 : case X7 : case F7 : case V7 : case CR7: case CR1UN: return 7;
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case R8 : case X8 : case F8 : case V8 : case CR2LT: return 8;
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case R9 : case X9 : case F9 : case V9 : case CR2GT: return 9;
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case R10: case X10: case F10: case V10: case CR2EQ: return 10;
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case R11: case X11: case F11: case V11: case CR2UN: return 11;
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case R12: case X12: case F12: case V12: case CR3LT: return 12;
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case R13: case X13: case F13: case V13: case CR3GT: return 13;
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case R14: case X14: case F14: case V14: case CR3EQ: return 14;
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case R15: case X15: case F15: case V15: case CR3UN: return 15;
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case R16: case X16: case F16: case V16: case CR4LT: return 16;
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case R17: case X17: case F17: case V17: case CR4GT: return 17;
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case R18: case X18: case F18: case V18: case CR4EQ: return 18;
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case R19: case X19: case F19: case V19: case CR4UN: return 19;
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case R20: case X20: case F20: case V20: case CR5LT: return 20;
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case R21: case X21: case F21: case V21: case CR5GT: return 21;
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case R22: case X22: case F22: case V22: case CR5EQ: return 22;
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case R23: case X23: case F23: case V23: case CR5UN: return 23;
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case R24: case X24: case F24: case V24: case CR6LT: return 24;
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case R25: case X25: case F25: case V25: case CR6GT: return 25;
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case R26: case X26: case F26: case V26: case CR6EQ: return 26;
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case R27: case X27: case F27: case V27: case CR6UN: return 27;
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case R28: case X28: case F28: case V28: case CR7LT: return 28;
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case R29: case X29: case F29: case V29: case CR7GT: return 29;
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case R30: case X30: case F30: case V30: case CR7EQ: return 30;
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case R31: case X31: case F31: case V31: case CR7UN: return 31;
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2006-07-11 22:53:55 +02:00
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default:
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2006-12-07 23:21:48 +01:00
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cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
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2006-07-11 22:53:55 +02:00
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abort();
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2006-04-17 23:07:20 +02:00
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}
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}
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2006-11-14 00:36:35 +01:00
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PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
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const TargetInstrInfo &tii)
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2006-07-11 02:48:23 +02:00
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: PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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2006-11-14 00:36:35 +01:00
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Subtarget(ST), TII(tii) {
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2005-04-22 01:30:14 +02:00
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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2004-08-17 06:55:41 +02:00
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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2005-10-18 02:28:58 +02:00
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ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
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2007-09-08 00:01:02 +02:00
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// 64-bit
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ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
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ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
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ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
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ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
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ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
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2004-08-17 06:55:41 +02:00
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}
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Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
llvm-svn: 40033
2007-07-19 03:14:50 +02:00
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const unsigned*
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PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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2006-07-11 02:48:23 +02:00
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// 32-bit Darwin calling convention.
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2007-04-03 14:35:28 +02:00
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static const unsigned Macho32_CalleeSavedRegs[] = {
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2006-11-16 23:43:37 +01:00
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PPC::R13, PPC::R14, PPC::R15,
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2006-07-11 02:48:23 +02:00
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31,
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PPC::F14, PPC::F15, PPC::F16, PPC::F17,
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PPC::F18, PPC::F19, PPC::F20, PPC::F21,
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PPC::F22, PPC::F23, PPC::F24, PPC::F25,
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PPC::F26, PPC::F27, PPC::F28, PPC::F29,
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PPC::F30, PPC::F31,
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PPC::CR2, PPC::CR3, PPC::CR4,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31,
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2008-03-10 15:12:10 +01:00
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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2006-07-11 02:48:23 +02:00
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PPC::LR, 0
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};
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2007-02-25 06:34:32 +01:00
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static const unsigned ELF32_CalleeSavedRegs[] = {
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PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31,
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2007-04-03 12:27:07 +02:00
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PPC::F9,
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PPC::F10, PPC::F11, PPC::F12, PPC::F13,
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2007-02-25 06:34:32 +01:00
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PPC::F14, PPC::F15, PPC::F16, PPC::F17,
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PPC::F18, PPC::F19, PPC::F20, PPC::F21,
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PPC::F22, PPC::F23, PPC::F24, PPC::F25,
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PPC::F26, PPC::F27, PPC::F28, PPC::F29,
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PPC::F30, PPC::F31,
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PPC::CR2, PPC::CR3, PPC::CR4,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31,
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2008-03-10 15:12:10 +01:00
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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2007-02-25 06:34:32 +01:00
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PPC::LR, 0
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};
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2006-07-11 02:48:23 +02:00
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// 64-bit Darwin calling convention.
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2007-04-03 14:35:28 +02:00
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static const unsigned Macho64_CalleeSavedRegs[] = {
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2006-11-20 20:33:51 +01:00
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PPC::X14, PPC::X15,
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2006-07-11 02:48:23 +02:00
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31,
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PPC::F14, PPC::F15, PPC::F16, PPC::F17,
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PPC::F18, PPC::F19, PPC::F20, PPC::F21,
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PPC::F22, PPC::F23, PPC::F24, PPC::F25,
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PPC::F26, PPC::F27, PPC::F28, PPC::F29,
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2006-05-18 02:12:58 +02:00
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PPC::F30, PPC::F31,
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2006-07-11 02:48:23 +02:00
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PPC::CR2, PPC::CR3, PPC::CR4,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31,
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2008-03-10 15:12:10 +01:00
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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2006-11-14 19:44:47 +01:00
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PPC::LR8, 0
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2006-05-18 02:12:58 +02:00
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};
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2006-07-11 02:48:23 +02:00
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2007-02-25 06:34:32 +01:00
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if (Subtarget.isMachoABI())
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2007-04-03 14:35:28 +02:00
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return Subtarget.isPPC64() ? Macho64_CalleeSavedRegs :
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Macho32_CalleeSavedRegs;
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2007-02-25 06:34:32 +01:00
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2007-04-03 14:35:28 +02:00
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// ELF 32.
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|
|
return ELF32_CalleeSavedRegs;
|
2006-05-18 02:12:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
const TargetRegisterClass* const*
|
2007-07-14 16:06:15 +02:00
|
|
|
PPCRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
|
2007-04-03 14:35:28 +02:00
|
|
|
// 32-bit Macho calling convention.
|
|
|
|
static const TargetRegisterClass * const Macho32_CalleeSavedRegClasses[] = {
|
2006-11-16 23:43:37 +01:00
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
2006-07-11 02:48:23 +02:00
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
|
|
|
|
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
|
|
|
|
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
|
2008-03-10 15:12:10 +01:00
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
|
2006-07-11 02:48:23 +02:00
|
|
|
&PPC::GPRCRegClass, 0
|
|
|
|
};
|
|
|
|
|
2007-02-25 06:34:32 +01:00
|
|
|
static const TargetRegisterClass * const ELF32_CalleeSavedRegClasses[] = {
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,&PPC::GPRCRegClass,
|
|
|
|
|
2007-04-03 12:57:49 +02:00
|
|
|
&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
2007-02-25 06:34:32 +01:00
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
|
|
|
|
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
|
|
|
|
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
|
2008-03-10 15:12:10 +01:00
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
|
2007-02-25 06:34:32 +01:00
|
|
|
&PPC::GPRCRegClass, 0
|
|
|
|
};
|
|
|
|
|
2007-04-03 14:35:28 +02:00
|
|
|
// 64-bit Macho calling convention.
|
|
|
|
static const TargetRegisterClass * const Macho64_CalleeSavedRegClasses[] = {
|
2006-11-20 20:33:51 +01:00
|
|
|
&PPC::G8RCRegClass,&PPC::G8RCRegClass,
|
2006-07-11 02:48:23 +02:00
|
|
|
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
|
|
|
|
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
|
|
|
|
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
|
|
|
|
&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,&PPC::G8RCRegClass,
|
|
|
|
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
&PPC::F8RCRegClass,&PPC::F8RCRegClass,
|
|
|
|
|
|
|
|
&PPC::CRRCRegClass,&PPC::CRRCRegClass,&PPC::CRRCRegClass,
|
|
|
|
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
|
|
|
|
|
2008-03-10 15:12:10 +01:00
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,&PPC::CRBITRCRegClass,
|
|
|
|
&PPC::CRBITRCRegClass,
|
|
|
|
|
2006-11-14 19:44:47 +01:00
|
|
|
&PPC::G8RCRegClass, 0
|
2006-05-18 02:12:58 +02:00
|
|
|
};
|
2007-02-25 06:34:32 +01:00
|
|
|
|
|
|
|
if (Subtarget.isMachoABI())
|
2007-04-03 14:35:28 +02:00
|
|
|
return Subtarget.isPPC64() ? Macho64_CalleeSavedRegClasses :
|
|
|
|
Macho32_CalleeSavedRegClasses;
|
2007-02-25 06:34:32 +01:00
|
|
|
|
2007-04-03 14:35:28 +02:00
|
|
|
// ELF 32.
|
|
|
|
return ELF32_CalleeSavedRegClasses;
|
2006-05-18 02:12:58 +02:00
|
|
|
}
|
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
// needsFP - Return true if the specified function should have a dedicated frame
|
|
|
|
// pointer register. This is true if the function has variable sized allocas or
|
|
|
|
// if frame pointer elimination is disabled.
|
|
|
|
//
|
|
|
|
static bool needsFP(const MachineFunction &MF) {
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
return NoFramePointerElim || MFI->hasVarSizedObjects();
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
static bool spillsCR(const MachineFunction &MF) {
|
|
|
|
const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
return FuncInfo->isCRSpilled();
|
|
|
|
}
|
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|
|
|
BitVector Reserved(getNumRegs());
|
|
|
|
Reserved.set(PPC::R0);
|
|
|
|
Reserved.set(PPC::R1);
|
|
|
|
Reserved.set(PPC::LR);
|
2008-03-03 23:19:16 +01:00
|
|
|
Reserved.set(PPC::LR8);
|
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
// In Linux, r2 is reserved for the OS.
|
|
|
|
if (!Subtarget.isDarwin())
|
|
|
|
Reserved.set(PPC::R2);
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
// On PPC64, r13 is the thread pointer. Never allocate this register. Note
|
|
|
|
// that this is over conservative, as it also prevents allocation of R31 when
|
|
|
|
// the FP is not needed.
|
2007-02-19 22:49:54 +01:00
|
|
|
if (Subtarget.isPPC64()) {
|
|
|
|
Reserved.set(PPC::R13);
|
|
|
|
Reserved.set(PPC::R31);
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2008-03-10 23:49:16 +01:00
|
|
|
if (!EnableRegisterScavenging)
|
2008-03-05 00:13:51 +01:00
|
|
|
Reserved.set(PPC::R0); // FIXME (64-bit): Remove
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
Reserved.set(PPC::X0);
|
|
|
|
Reserved.set(PPC::X1);
|
|
|
|
Reserved.set(PPC::X13);
|
|
|
|
Reserved.set(PPC::X31);
|
2007-02-19 22:49:54 +01:00
|
|
|
}
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
if (needsFP(MF))
|
|
|
|
Reserved.set(PPC::R31);
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2007-02-19 22:49:54 +01:00
|
|
|
return Reserved;
|
|
|
|
}
|
|
|
|
|
2004-08-17 06:55:41 +02:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Stack Frame Processing methods
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// hasFP - Return true if the specified function actually has a dedicated frame
|
|
|
|
// pointer register. This is true if the function needs a frame pointer and has
|
|
|
|
// a non-zero stack size.
|
2007-01-23 01:57:47 +01:00
|
|
|
bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
|
2006-11-16 23:43:37 +01:00
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
return MFI->getStackSize() && needsFP(MF);
|
|
|
|
}
|
|
|
|
|
2007-12-08 07:39:11 +01:00
|
|
|
/// MustSaveLR - Return true if this function requires that we save the LR
|
2007-12-08 07:59:59 +01:00
|
|
|
/// register onto the stack in the prolog and restore it in the epilog of the
|
|
|
|
/// function.
|
2007-12-08 07:39:11 +01:00
|
|
|
static bool MustSaveLR(const MachineFunction &MF) {
|
2007-12-08 07:59:59 +01:00
|
|
|
const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
|
|
|
|
// We need an save/restore of LR if there is any use/def of LR explicitly, or
|
|
|
|
// if there is some use of the LR stack slot (e.g. for builtin_return_address.
|
|
|
|
return MFI->usesLR() || MFI->isLRStoreRequired() ||
|
2007-12-08 07:39:11 +01:00
|
|
|
// FIXME: Anything that has a call should clobber the LR register,
|
|
|
|
// isn't this redundant??
|
|
|
|
MF.getFrameInfo()->hasCalls();
|
2006-12-06 18:42:06 +01:00
|
|
|
}
|
|
|
|
|
2005-10-16 07:39:50 +02:00
|
|
|
void PPCRegisterInfo::
|
2004-08-17 06:55:41 +02:00
|
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator I) const {
|
2006-11-16 23:43:37 +01:00
|
|
|
// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
|
2004-08-17 06:55:41 +02:00
|
|
|
MBB.erase(I);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
/// findScratchRegister - Find a 'free' PPC register. Try for a call-clobbered
|
|
|
|
/// register first and then a spilled callee-saved register if that fails.
|
|
|
|
static
|
|
|
|
unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS,
|
|
|
|
const TargetRegisterClass *RC, int SPAdj) {
|
|
|
|
assert(RS && "Register scavenging must be on");
|
|
|
|
unsigned Reg = RS->FindUnusedReg(RC, true);
|
|
|
|
// FIXME: move ARM callee-saved reg scan to target independent code, then
|
|
|
|
// search for already spilled CS register here.
|
|
|
|
if (Reg == 0)
|
|
|
|
Reg = RS->scavengeRegister(RC, II, SPAdj);
|
|
|
|
return Reg;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// lowerDynamicAlloc - Generate the code for allocating an object in the
|
2006-11-16 23:43:37 +01:00
|
|
|
/// current frame. The sequence of code with be in the general form
|
|
|
|
///
|
|
|
|
/// addi R0, SP, #frameSize ; get the address of the previous frame
|
|
|
|
/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
|
|
|
|
/// addi Rnew, SP, #maxCalFrameSize ; get the top of the allocation
|
|
|
|
///
|
2008-03-03 23:19:16 +01:00
|
|
|
void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
|
|
|
|
int SPAdj, RegScavenger *RS) const {
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II;
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
// Get the basic block's function.
|
|
|
|
MachineFunction &MF = *MBB.getParent();
|
|
|
|
// Get the frame info.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Determine whether 64-bit pointers are used.
|
|
|
|
bool LP64 = Subtarget.isPPC64();
|
|
|
|
|
2007-01-25 23:48:25 +01:00
|
|
|
// Get the maximum call stack size.
|
2006-11-16 23:43:37 +01:00
|
|
|
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
|
|
|
|
// Get the total frame size.
|
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
// Get stack alignments.
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2006-11-17 19:49:39 +01:00
|
|
|
assert(MaxAlign <= TargetAlign &&
|
|
|
|
"Dynamic alloca with large aligns not supported");
|
2006-11-16 23:43:37 +01:00
|
|
|
|
|
|
|
// Determine the previous frame's address. If FrameSize can't be
|
|
|
|
// represented as 16 bits or we need special alignment, then we load the
|
|
|
|
// previous frame's address from 0(SP). Why not do an addis of the hi?
|
|
|
|
// Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
|
|
|
|
// Constructing the constant and adding would take 3 instructions.
|
|
|
|
// Fortunately, a frame greater than 32K is rare.
|
2008-03-03 23:19:16 +01:00
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
const TargetRegisterClass *RC = LP64 ? G8RC : GPRC;
|
|
|
|
|
|
|
|
// FIXME (64-bit): Use "findScratchRegister"
|
|
|
|
unsigned Reg;
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging)
|
2008-03-03 23:19:16 +01:00
|
|
|
Reg = findScratchRegister(II, RS, RC, SPAdj);
|
|
|
|
else
|
|
|
|
Reg = PPC::R0;
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
if (MaxAlign < TargetAlign && isInt16(FrameSize)) {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, II, TII.get(PPC::ADDI), Reg)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addReg(PPC::R31)
|
|
|
|
.addImm(FrameSize);
|
|
|
|
} else if (LP64) {
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
|
2008-03-05 00:13:51 +01:00
|
|
|
BuildMI(MBB, II, TII.get(PPC::LD), Reg)
|
2008-03-20 02:22:40 +01:00
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::X1);
|
2008-03-05 00:13:51 +01:00
|
|
|
else
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0)
|
2008-03-20 02:22:40 +01:00
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::X1);
|
2006-11-16 23:43:37 +01:00
|
|
|
} else {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, II, TII.get(PPC::LWZ), Reg)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(0)
|
|
|
|
.addReg(PPC::R1);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// Grow the stack and update the stack pointer link, then determine the
|
|
|
|
// address of new allocated space.
|
2006-11-16 23:43:37 +01:00
|
|
|
if (LP64) {
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part.
|
2008-03-05 00:13:51 +01:00
|
|
|
BuildMI(MBB, II, TII.get(PPC::STDUX))
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(Reg, false, false, true)
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-05 00:13:51 +01:00
|
|
|
else
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::STDUX))
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::X0, false, false, true)
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
if (!MI.getOperand(1).isKill())
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 23:19:16 +01:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(maxCallFrameSize)
|
|
|
|
.addReg(MI.getOperand(1).getReg(), false, true, true);
|
2006-11-16 23:43:37 +01:00
|
|
|
} else {
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, II, TII.get(PPC::STWUX))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(Reg, false, false, true)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addReg(MI.getOperand(1).getReg());
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
if (!MI.getOperand(1).isKill())
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize);
|
2008-03-03 23:19:16 +01:00
|
|
|
else
|
|
|
|
// Implicitly kill the register.
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
|
2008-03-20 02:22:40 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(maxCallFrameSize)
|
|
|
|
.addReg(MI.getOperand(1).getReg(), false, true, true);
|
2006-11-16 23:43:37 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Discard the DYNALLOC instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
|
|
|
|
/// reserving a whole register (R0), we scrounge for one here. This generates
|
|
|
|
/// code like this:
|
|
|
|
///
|
|
|
|
/// mfcr rA ; Move the conditional register into GPR rA.
|
|
|
|
/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
|
|
|
|
/// stw rA, FI ; Store rA to the frame.
|
|
|
|
///
|
|
|
|
void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
|
|
|
|
unsigned FrameIndex, int SPAdj,
|
|
|
|
RegScavenger *RS) const {
|
|
|
|
// Get the instruction.
|
|
|
|
MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
|
|
|
|
// Get the instruction's basic block.
|
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
|
|
|
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
|
|
|
|
unsigned Reg = findScratchRegister(II, RS, RC, SPAdj);
|
|
|
|
|
2008-03-05 00:27:33 +01:00
|
|
|
// We need to store the CR in the low 4-bits of the saved value. First, issue
|
|
|
|
// an MFCR to save all of the CRBits. Add an implicit kill of the CR.
|
2008-03-03 23:19:16 +01:00
|
|
|
if (!MI.getOperand(0).isKill())
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::MFCR), Reg);
|
|
|
|
else
|
|
|
|
// Implicitly kill the CR register.
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::MFCR), Reg)
|
|
|
|
.addReg(MI.getOperand(0).getReg(), false, true, true);
|
2008-03-05 00:27:33 +01:00
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// If the saved register wasn't CR0, shift the bits left so that they are in
|
|
|
|
// CR0's slot.
|
|
|
|
unsigned SrcReg = MI.getOperand(0).getReg();
|
|
|
|
if (SrcReg != PPC::CR0)
|
|
|
|
// rlwinm rA, rA, ShiftBits, 0, 31.
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::RLWINM), Reg)
|
|
|
|
.addReg(Reg, false, false, true)
|
|
|
|
.addImm(PPCRegisterInfo::getRegisterNumbering(SrcReg) * 4)
|
|
|
|
.addImm(0)
|
|
|
|
.addImm(31);
|
|
|
|
|
|
|
|
addFrameReference(BuildMI(MBB, II, TII.get(PPC::STW))
|
|
|
|
.addReg(Reg, false, false, MI.getOperand(1).getImm()),
|
|
|
|
FrameIndex);
|
|
|
|
|
|
|
|
// Discard the pseudo instruction.
|
|
|
|
MBB.erase(II);
|
|
|
|
}
|
|
|
|
|
2007-02-28 01:21:17 +01:00
|
|
|
void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
2007-05-01 11:13:03 +02:00
|
|
|
int SPAdj, RegScavenger *RS) const {
|
|
|
|
assert(SPAdj == 0 && "Unexpected");
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the instruction.
|
2004-08-17 06:55:41 +02:00
|
|
|
MachineInstr &MI = *II;
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the instruction's basic block.
|
2004-08-17 06:55:41 +02:00
|
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the basic block's function.
|
2004-08-17 06:55:41 +02:00
|
|
|
MachineFunction &MF = *MBB.getParent();
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the frame info.
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2005-04-22 01:30:14 +02:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Find out which operand is the frame index.
|
2007-10-16 20:00:18 +02:00
|
|
|
unsigned FIOperandNo = 0;
|
|
|
|
while (!MI.getOperand(FIOperandNo).isFrameIndex()) {
|
|
|
|
++FIOperandNo;
|
|
|
|
assert(FIOperandNo != MI.getNumOperands() &&
|
|
|
|
"Instr doesn't have FrameIndex operand!");
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
2006-11-16 23:43:37 +01:00
|
|
|
// Take into account whether it's an add or mem instruction
|
2007-10-16 20:00:18 +02:00
|
|
|
unsigned OffsetOperandNo = (FIOperandNo == 2) ? 1 : 2;
|
2007-02-01 01:39:08 +01:00
|
|
|
if (MI.getOpcode() == TargetInstrInfo::INLINEASM)
|
2007-10-16 20:00:18 +02:00
|
|
|
OffsetOperandNo = FIOperandNo-1;
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the frame index.
|
2007-12-31 00:10:15 +01:00
|
|
|
int FrameIndex = MI.getOperand(FIOperandNo).getIndex();
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get the frame pointer save index. Users of this index are primarily
|
|
|
|
// DYNALLOC instructions.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
|
|
// Get the instruction opcode.
|
|
|
|
unsigned OpC = MI.getOpcode();
|
|
|
|
|
|
|
|
// Special case for dynamic alloca.
|
|
|
|
if (FPSI && FrameIndex == FPSI &&
|
|
|
|
(OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
|
2008-03-03 23:19:16 +01:00
|
|
|
lowerDynamicAlloc(II, SPAdj, RS);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Special case for pseudo-op SPILL_CR.
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
|
2008-03-05 00:13:51 +01:00
|
|
|
if (OpC == PPC::SPILL_CR) {
|
|
|
|
lowerCRSpilling(II, FrameIndex, SPAdj, RS);
|
|
|
|
return;
|
|
|
|
}
|
2004-08-17 06:55:41 +02:00
|
|
|
|
|
|
|
// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
|
2007-10-16 20:00:18 +02:00
|
|
|
MI.getOperand(FIOperandNo).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1,
|
|
|
|
false);
|
2004-08-17 06:55:41 +02:00
|
|
|
|
2006-06-27 20:55:49 +02:00
|
|
|
// Figure out if the offset in the instruction is shifted right two bits. This
|
|
|
|
// is true for instructions like "STD", which the machine implicitly adds two
|
|
|
|
// low zeros to.
|
|
|
|
bool isIXAddr = false;
|
2006-11-16 23:43:37 +01:00
|
|
|
switch (OpC) {
|
2006-06-27 20:55:49 +02:00
|
|
|
case PPC::LWA:
|
|
|
|
case PPC::LD:
|
|
|
|
case PPC::STD:
|
|
|
|
case PPC::STD_32:
|
|
|
|
isIXAddr = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2004-08-17 06:55:41 +02:00
|
|
|
// Now add the frame object offset to the offset from r1.
|
2006-11-16 23:43:37 +01:00
|
|
|
int Offset = MFI->getObjectOffset(FrameIndex);
|
2006-06-27 20:55:49 +02:00
|
|
|
if (!isIXAddr)
|
2007-12-30 21:49:49 +01:00
|
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm();
|
2006-06-27 20:55:49 +02:00
|
|
|
else
|
2007-12-30 21:49:49 +01:00
|
|
|
Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
|
2004-08-17 06:55:41 +02:00
|
|
|
|
|
|
|
// If we're not using a Frame Pointer that has been set to the value of the
|
|
|
|
// SP before having the stack size subtracted from it, then add the stack size
|
|
|
|
// to Offset to get the correct offset.
|
2006-11-16 23:43:37 +01:00
|
|
|
Offset += MFI->getStackSize();
|
2005-04-22 01:30:14 +02:00
|
|
|
|
2007-11-27 23:14:42 +01:00
|
|
|
// If we can, encode the offset directly into the instruction. If this is a
|
|
|
|
// normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
|
|
|
|
// this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
|
|
|
|
// clear can be encoded. This is extremely uncommon, because normally you
|
|
|
|
// only "std" to a stack slot that is at least 4-byte aligned, but it can
|
|
|
|
// happen in invalid code.
|
Fix a significant code quality regression I introduced on PPC64 quite
a while ago. We now produce:
_foo:
mflr r0
std r0, 16(r1)
ld r2, 16(r1)
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
instead of:
_foo:
mflr r0
std r0, 16(r1)
lis r0, 0
ori r0, r0, 16
ldx r2, r1, r0
std r2, 0(r3)
ld r0, 16(r1)
mtlr r0
blr
for:
void foo(void **X) {
*X = __builtin_return_address(0);
}
on ppc64.
llvm-svn: 44701
2007-12-08 08:04:58 +01:00
|
|
|
if (isInt16(Offset) && (!isIXAddr || (Offset & 3) == 0)) {
|
2007-11-27 23:14:42 +01:00
|
|
|
if (isIXAddr)
|
2007-10-16 20:00:18 +02:00
|
|
|
Offset >>= 2; // The actual encoded value has the low two bits zero.
|
|
|
|
MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
|
2007-11-27 23:14:42 +01:00
|
|
|
return;
|
|
|
|
}
|
2008-03-03 23:19:16 +01:00
|
|
|
|
|
|
|
// The offset doesn't fit into a single register, scavenge one to build the
|
|
|
|
// offset in.
|
|
|
|
// FIXME: figure out what SPAdj is doing here.
|
|
|
|
|
|
|
|
// FIXME (64-bit): Use "findScratchRegister".
|
|
|
|
unsigned SReg;
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging)
|
2008-03-03 23:19:16 +01:00
|
|
|
SReg = findScratchRegister(II, RS, &PPC::GPRCRegClass, SPAdj);
|
|
|
|
else
|
|
|
|
SReg = PPC::R0;
|
|
|
|
|
|
|
|
// Insert a set of rA with the full offset value before the ld, st, or add
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::LIS), SReg)
|
|
|
|
.addImm(Offset >> 16);
|
|
|
|
BuildMI(MBB, II, TII.get(PPC::ORI), SReg)
|
|
|
|
.addReg(SReg, false, false, true)
|
|
|
|
.addImm(Offset);
|
|
|
|
|
|
|
|
// Convert into indexed form of the instruction:
|
|
|
|
//
|
|
|
|
// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
|
|
|
|
// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
|
2007-11-27 23:14:42 +01:00
|
|
|
unsigned OperandBase;
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2007-11-27 23:14:42 +01:00
|
|
|
if (OpC != TargetInstrInfo::INLINEASM) {
|
|
|
|
assert(ImmToIdxMap.count(OpC) &&
|
|
|
|
"No indexed form of load or store available!");
|
|
|
|
unsigned NewOpcode = ImmToIdxMap.find(OpC)->second;
|
2008-01-11 19:10:50 +01:00
|
|
|
MI.setDesc(TII.get(NewOpcode));
|
2007-11-27 23:14:42 +01:00
|
|
|
OperandBase = 1;
|
2007-10-16 20:00:18 +02:00
|
|
|
} else {
|
2007-11-27 23:14:42 +01:00
|
|
|
OperandBase = OffsetOperandNo;
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
2007-11-27 23:14:42 +01:00
|
|
|
|
|
|
|
unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
|
|
|
|
MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
|
2008-03-03 23:19:16 +01:00
|
|
|
MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
|
|
|
|
2006-04-17 22:59:25 +02:00
|
|
|
/// VRRegNo - Map from a numbered VR register to its enum value.
|
|
|
|
///
|
|
|
|
static const unsigned short VRRegNo[] = {
|
2006-06-12 23:50:57 +02:00
|
|
|
PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
|
|
|
|
PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
|
2006-04-17 22:59:25 +02:00
|
|
|
PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
|
|
|
|
PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
|
|
|
|
};
|
|
|
|
|
2006-04-17 23:48:13 +02:00
|
|
|
/// RemoveVRSaveCode - We have found that this function does not need any code
|
|
|
|
/// to manipulate the VRSAVE register, even though it uses vector registers.
|
|
|
|
/// This can happen when the only registers used are known to be live in or out
|
|
|
|
/// of the function. Remove all of the VRSAVE related code from the function.
|
|
|
|
static void RemoveVRSaveCode(MachineInstr *MI) {
|
|
|
|
MachineBasicBlock *Entry = MI->getParent();
|
|
|
|
MachineFunction *MF = Entry->getParent();
|
|
|
|
|
|
|
|
// We know that the MTVRSAVE instruction immediately follows MI. Remove it.
|
|
|
|
MachineBasicBlock::iterator MBBI = MI;
|
|
|
|
++MBBI;
|
|
|
|
assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
|
|
|
|
MBBI->eraseFromParent();
|
|
|
|
|
|
|
|
bool RemovedAllMTVRSAVEs = true;
|
|
|
|
// See if we can find and remove the MTVRSAVE instruction from all of the
|
|
|
|
// epilog blocks.
|
|
|
|
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
|
|
|
|
// If last instruction is a return instruction, add an epilogue
|
2008-01-07 08:27:27 +01:00
|
|
|
if (!I->empty() && I->back().getDesc().isReturn()) {
|
2006-04-17 23:48:13 +02:00
|
|
|
bool FoundIt = false;
|
|
|
|
for (MBBI = I->end(); MBBI != I->begin(); ) {
|
|
|
|
--MBBI;
|
|
|
|
if (MBBI->getOpcode() == PPC::MTVRSAVE) {
|
|
|
|
MBBI->eraseFromParent(); // remove it.
|
|
|
|
FoundIt = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
RemovedAllMTVRSAVEs &= FoundIt;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we found and removed all MTVRSAVE instructions, remove the read of
|
|
|
|
// VRSAVE as well.
|
|
|
|
if (RemovedAllMTVRSAVEs) {
|
|
|
|
MBBI = MI;
|
|
|
|
assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
|
|
|
|
--MBBI;
|
|
|
|
assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
|
|
|
|
MBBI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, nuke the UPDATE_VRSAVE.
|
|
|
|
MI->eraseFromParent();
|
|
|
|
}
|
|
|
|
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
|
|
|
|
// instruction selector. Based on the vector registers that have been used,
|
|
|
|
// transform this into the appropriate ORI instruction.
|
2007-04-26 00:13:27 +02:00
|
|
|
static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
|
|
|
|
MachineFunction *MF = MI->getParent()->getParent();
|
|
|
|
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
unsigned UsedRegMask = 0;
|
2006-04-17 22:59:25 +02:00
|
|
|
for (unsigned i = 0; i != 32; ++i)
|
2007-12-31 05:13:23 +01:00
|
|
|
if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
|
2006-04-17 22:59:25 +02:00
|
|
|
UsedRegMask |= 1 << (31-i);
|
|
|
|
|
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 23:22:06 +02:00
|
|
|
// Live in and live out values already must be in the mask, so don't bother
|
|
|
|
// marking them.
|
2007-12-31 05:13:23 +01:00
|
|
|
for (MachineRegisterInfo::livein_iterator
|
|
|
|
I = MF->getRegInfo().livein_begin(),
|
|
|
|
E = MF->getRegInfo().livein_end(); I != E; ++I) {
|
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 23:22:06 +02:00
|
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
|
|
|
|
if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
|
|
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
|
|
}
|
2007-12-31 05:13:23 +01:00
|
|
|
for (MachineRegisterInfo::liveout_iterator
|
|
|
|
I = MF->getRegInfo().liveout_begin(),
|
|
|
|
E = MF->getRegInfo().liveout_end(); I != E; ++I) {
|
Vectors that are known live-in and live-out are clearly already marked in
the vrsave register for the caller. This allows us to codegen a function as:
_test_rol:
mfspr r2, 256
mr r3, r2
mtspr 256, r3
vspltisw v2, -12
vrlw v2, v2, v2
mtspr 256, r2
blr
instead of:
_test_rol:
mfspr r2, 256
oris r3, r2, 40960
mtspr 256, r3
vspltisw v0, -12
vrlw v2, v0, v0
mtspr 256, r2
blr
llvm-svn: 27772
2006-04-17 23:22:06 +02:00
|
|
|
unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
|
|
|
|
if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
|
|
|
|
UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
|
|
|
|
}
|
|
|
|
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
// If no registers are used, turn this into a copy.
|
|
|
|
if (UsedRegMask == 0) {
|
2006-04-17 23:48:13 +02:00
|
|
|
// Remove all VRSAVE code.
|
|
|
|
RemoveVRSaveCode(MI);
|
|
|
|
return;
|
2008-03-03 23:19:16 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
|
|
|
|
|
|
if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
|
|
|
|
if (DstReg != SrcReg)
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(UsedRegMask);
|
|
|
|
else
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
|
|
|
|
.addReg(SrcReg, false, false, true)
|
|
|
|
.addImm(UsedRegMask);
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
} else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
|
2008-03-03 23:19:16 +01:00
|
|
|
if (DstReg != SrcReg)
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(UsedRegMask >> 16);
|
|
|
|
else
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
|
|
|
|
.addReg(SrcReg, false, false, true)
|
|
|
|
.addImm(UsedRegMask >> 16);
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
} else {
|
2008-03-03 23:19:16 +01:00
|
|
|
if (DstReg != SrcReg)
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
|
|
|
|
.addReg(SrcReg)
|
|
|
|
.addImm(UsedRegMask >> 16);
|
|
|
|
else
|
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORIS), DstReg)
|
|
|
|
.addReg(SrcReg, false, false, true)
|
|
|
|
.addImm(UsedRegMask >> 16);
|
|
|
|
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(*MI->getParent(), MI, TII.get(PPC::ORI), DstReg)
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(DstReg, false, false, true)
|
|
|
|
.addImm(UsedRegMask & 0xFFFF);
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// Remove the old UPDATE_VRSAVE instruction.
|
2006-04-17 23:48:13 +02:00
|
|
|
MI->eraseFromParent();
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
}
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
/// determineFrameLayout - Determine the size of the frame and maximum call
|
|
|
|
/// frame size.
|
|
|
|
void PPCRegisterInfo::determineFrameLayout(MachineFunction &MF) const {
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
|
|
|
|
|
|
|
// Get the alignments provided by the target, and the maximum alignment
|
|
|
|
// (if any) of the fixed frame objects.
|
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2007-01-25 23:25:04 +01:00
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
unsigned AlignMask = TargetAlign - 1; //
|
2006-11-16 23:43:37 +01:00
|
|
|
|
|
|
|
// If we are a leaf function, and use up to 224 bytes of stack space,
|
|
|
|
// don't have a frame pointer, calls, or dynamic alloca then we do not need
|
|
|
|
// to adjust the stack pointer (we fit in the Red Zone).
|
2008-03-10 23:59:46 +01:00
|
|
|
if (FrameSize <= 224 && // Fits in red zone.
|
|
|
|
!MFI->hasVarSizedObjects() && // No dynamic alloca.
|
|
|
|
!MFI->hasCalls() && // No calls.
|
|
|
|
(!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
|
2006-11-16 23:43:37 +01:00
|
|
|
// No need for frame
|
|
|
|
MFI->setStackSize(0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Get the maximum call frame size of all the calls.
|
|
|
|
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
|
|
|
|
|
|
|
|
// Maximum call frame needs to be at least big enough for linkage and 8 args.
|
|
|
|
unsigned minCallFrameSize =
|
2007-02-25 06:34:32 +01:00
|
|
|
PPCFrameInfo::getMinCallFrameSize(Subtarget.isPPC64(),
|
|
|
|
Subtarget.isMachoABI());
|
2006-11-16 23:43:37 +01:00
|
|
|
maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
|
|
|
|
|
|
|
|
// If we have dynamic alloca then maxCallFrameSize needs to be aligned so
|
|
|
|
// that allocations will be aligned.
|
|
|
|
if (MFI->hasVarSizedObjects())
|
|
|
|
maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
|
|
|
|
|
|
|
|
// Update maximum call frame size.
|
|
|
|
MFI->setMaxCallFrameSize(maxCallFrameSize);
|
|
|
|
|
|
|
|
// Include call frame size in total.
|
|
|
|
FrameSize += maxCallFrameSize;
|
2007-02-25 06:34:32 +01:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Make sure the frame is aligned.
|
|
|
|
FrameSize = (FrameSize + AlignMask) & ~AlignMask;
|
|
|
|
|
|
|
|
// Update frame info.
|
|
|
|
MFI->setStackSize(FrameSize);
|
|
|
|
}
|
2004-08-17 06:55:41 +02:00
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
void
|
|
|
|
PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
|
|
RegScavenger *RS) const {
|
2007-02-27 12:55:45 +01:00
|
|
|
// Save and clear the LR state.
|
|
|
|
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
|
|
|
|
unsigned LR = getRARegister();
|
2007-12-31 05:13:23 +01:00
|
|
|
FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
|
|
|
|
MF.getRegInfo().setPhysRegUnused(LR);
|
2007-03-21 17:44:14 +01:00
|
|
|
|
|
|
|
// Save R31 if necessary
|
|
|
|
int FPSI = FI->getFramePointerSaveIndex();
|
|
|
|
bool IsPPC64 = Subtarget.isPPC64();
|
2007-04-03 14:35:28 +02:00
|
|
|
bool IsELF32_ABI = Subtarget.isELF32_ABI();
|
|
|
|
bool IsMachoABI = Subtarget.isMachoABI();
|
2008-03-03 23:19:16 +01:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-03-21 17:44:14 +01:00
|
|
|
|
|
|
|
// If the frame pointer save index hasn't been defined yet.
|
2007-12-31 05:13:23 +01:00
|
|
|
if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
|
|
|
|
IsELF32_ABI) {
|
2007-03-21 17:44:14 +01:00
|
|
|
// Find out what the fix offset of the frame pointer save area.
|
2007-04-03 14:35:28 +02:00
|
|
|
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
|
|
|
|
IsMachoABI);
|
2007-03-21 17:44:14 +01:00
|
|
|
// Allocate the frame index for frame pointer save area.
|
|
|
|
FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
|
|
|
|
// Save the result.
|
|
|
|
FI->setFramePointerSaveIndex(FPSI);
|
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
// Reserve a slot closest to SP or frame pointer if we have a dynalloc or
|
|
|
|
// a large stack, which will require scavenging a register to materialize a
|
|
|
|
// large offset.
|
|
|
|
// FIXME: this doesn't actually check stack size, so is a bit pessimistic
|
|
|
|
// FIXME: doesn't detect whether or not we need to spill vXX, which requires
|
|
|
|
// r0 for now.
|
|
|
|
|
2008-03-10 23:49:16 +01:00
|
|
|
if (EnableRegisterScavenging) // FIXME (64-bit): Enable.
|
2008-03-05 00:13:51 +01:00
|
|
|
if (needsFP(MF) || spillsCR(MF)) {
|
|
|
|
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
|
|
|
|
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
|
|
|
|
const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
|
|
|
|
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
|
2008-03-20 02:22:40 +01:00
|
|
|
RC->getAlignment()));
|
2008-03-05 00:13:51 +01:00
|
|
|
}
|
2007-02-27 12:55:45 +01:00
|
|
|
}
|
|
|
|
|
2008-03-03 23:19:16 +01:00
|
|
|
void
|
|
|
|
PPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
|
2004-08-17 06:55:41 +02:00
|
|
|
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
|
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-01-26 22:22:28 +01:00
|
|
|
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
2008-04-02 19:04:45 +02:00
|
|
|
bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) ||
|
2008-04-08 02:10:24 +02:00
|
|
|
!MF.getFunction()->doesNotThrow() ||
|
2008-04-14 19:54:17 +02:00
|
|
|
UnwindTablesMandatory;
|
2006-04-04 00:03:29 +02:00
|
|
|
|
2007-01-29 19:51:14 +01:00
|
|
|
// Prepare for frame info.
|
2007-01-24 19:45:13 +01:00
|
|
|
unsigned FrameLabelId = 0;
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-04-04 00:03:29 +02:00
|
|
|
// Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
|
|
|
|
// process it.
|
2006-03-16 22:31:45 +01:00
|
|
|
for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
|
2007-04-26 00:13:27 +02:00
|
|
|
HandleVRSaveUpdate(MBBI, TII);
|
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
llvm-svn: 26733
2006-03-13 22:52:10 +01:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// Move MBBI back to the beginning of the function.
|
|
|
|
MBBI = MBB.begin();
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Work out frame sizes.
|
|
|
|
determineFrameLayout(MF);
|
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
2005-11-06 10:00:38 +01:00
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
int NegFrameSize = -FrameSize;
|
2006-12-06 18:42:06 +01:00
|
|
|
|
|
|
|
// Get processor type.
|
|
|
|
bool IsPPC64 = Subtarget.isPPC64();
|
2007-02-25 06:34:32 +01:00
|
|
|
// Get operating system
|
|
|
|
bool IsMachoABI = Subtarget.isMachoABI();
|
2006-12-06 18:42:06 +01:00
|
|
|
// Check if the link register (LR) has been used.
|
2007-12-08 07:39:11 +01:00
|
|
|
bool UsesLR = MustSaveLR(MF);
|
2006-11-16 23:43:37 +01:00
|
|
|
// Do we have a frame pointer for this function?
|
2007-02-27 12:55:45 +01:00
|
|
|
bool HasFP = hasFP(MF) && FrameSize;
|
2006-12-06 18:42:06 +01:00
|
|
|
|
2007-02-25 06:34:32 +01:00
|
|
|
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
|
|
|
|
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-12-06 18:42:06 +01:00
|
|
|
if (IsPPC64) {
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::MFLR8), PPC::X0);
|
|
|
|
|
|
|
|
if (HasFP)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STD))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::X31)
|
|
|
|
.addImm(FPOffset/4)
|
|
|
|
.addReg(PPC::X1);
|
2006-12-06 18:42:06 +01:00
|
|
|
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STD))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::X0)
|
|
|
|
.addImm(LROffset / 4)
|
|
|
|
.addReg(PPC::X1);
|
2006-12-06 18:42:06 +01:00
|
|
|
} else {
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::MFLR), PPC::R0);
|
|
|
|
|
|
|
|
if (HasFP)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STW))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::R31)
|
|
|
|
.addImm(FPOffset)
|
|
|
|
.addReg(PPC::R1);
|
2004-08-17 06:55:41 +02:00
|
|
|
|
2006-12-06 18:42:06 +01:00
|
|
|
if (UsesLR)
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STW))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::R0)
|
|
|
|
.addImm(LROffset)
|
|
|
|
.addReg(PPC::R1);
|
2005-07-27 08:06:29 +02:00
|
|
|
}
|
2006-11-16 23:43:37 +01:00
|
|
|
|
2007-02-27 12:55:45 +01:00
|
|
|
// Skip if a leaf routine.
|
|
|
|
if (!FrameSize) return;
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Get stack alignments.
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2004-08-17 06:55:41 +02:00
|
|
|
|
2008-04-02 19:04:45 +02:00
|
|
|
if (needsFrameMoves) {
|
2007-01-24 19:45:13 +01:00
|
|
|
// Mark effective beginning of when frame pointer becomes valid.
|
2007-01-26 22:22:28 +01:00
|
|
|
FrameLabelId = MMI->NextLabelID();
|
2008-01-31 10:59:15 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
|
2007-01-24 19:45:13 +01:00
|
|
|
}
|
|
|
|
|
2006-11-16 23:43:37 +01:00
|
|
|
// Adjust stack pointer: r1 += NegFrameSize.
|
2006-04-11 21:29:21 +02:00
|
|
|
// If there is a preferred stack alignment, align R1 now
|
2006-12-06 18:42:06 +01:00
|
|
|
if (!IsPPC64) {
|
2006-11-11 20:05:28 +01:00
|
|
|
// PPC32.
|
2008-03-10 23:59:46 +01:00
|
|
|
if (ALIGN_STACK && MaxAlign > TargetAlign) {
|
2006-11-16 23:43:37 +01:00
|
|
|
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
|
|
|
|
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::RLWINM), PPC::R0)
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(0)
|
|
|
|
.addImm(32 - Log2_32(MaxAlign))
|
|
|
|
.addImm(31);
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC) ,PPC::R0)
|
|
|
|
.addReg(PPC::R0, false, false, true)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(NegFrameSize);
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addReg(PPC::R0);
|
2006-11-16 23:43:37 +01:00
|
|
|
} else if (isInt16(NegFrameSize)) {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STWU), PPC::R1)
|
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addImm(NegFrameSize)
|
|
|
|
.addReg(PPC::R1);
|
2006-11-11 20:05:28 +01:00
|
|
|
} else {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LIS), PPC::R0)
|
|
|
|
.addImm(NegFrameSize >> 16);
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::ORI), PPC::R0)
|
|
|
|
.addReg(PPC::R0, false, false, true)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(NegFrameSize & 0xFFFF);
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STWUX))
|
|
|
|
.addReg(PPC::R1)
|
|
|
|
.addReg(PPC::R1)
|
2006-11-11 20:05:28 +01:00
|
|
|
.addReg(PPC::R0);
|
|
|
|
}
|
|
|
|
} else { // PPC64.
|
2008-03-10 23:59:46 +01:00
|
|
|
if (ALIGN_STACK && MaxAlign > TargetAlign) {
|
2006-11-16 23:43:37 +01:00
|
|
|
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
|
|
|
|
assert(isInt16(NegFrameSize) && "Unhandled stack size and alignment!");
|
2008-03-03 23:19:16 +01:00
|
|
|
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::RLDICL), PPC::X0)
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(0)
|
|
|
|
.addImm(64 - Log2_32(MaxAlign));
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::SUBFIC8), PPC::X0)
|
|
|
|
.addReg(PPC::X0)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(NegFrameSize);
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(PPC::X0);
|
2006-11-17 17:09:31 +01:00
|
|
|
} else if (isInt16(NegFrameSize)) {
|
2006-11-28 00:37:22 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STDU), PPC::X1)
|
2008-03-03 23:19:16 +01:00
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addImm(NegFrameSize / 4)
|
|
|
|
.addReg(PPC::X1);
|
2006-11-11 20:05:28 +01:00
|
|
|
} else {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LIS8), PPC::X0)
|
|
|
|
.addImm(NegFrameSize >> 16);
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::ORI8), PPC::X0)
|
|
|
|
.addReg(PPC::X0, false, false, true)
|
2006-11-16 23:43:37 +01:00
|
|
|
.addImm(NegFrameSize & 0xFFFF);
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::STDUX))
|
|
|
|
.addReg(PPC::X1)
|
|
|
|
.addReg(PPC::X1)
|
2006-11-11 20:05:28 +01:00
|
|
|
.addReg(PPC::X0);
|
|
|
|
}
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
2005-11-06 10:00:38 +01:00
|
|
|
|
2008-04-02 19:04:45 +02:00
|
|
|
if (needsFrameMoves) {
|
2007-01-26 22:22:28 +01:00
|
|
|
std::vector<MachineMove> &Moves = MMI->getFrameMoves();
|
2006-04-07 18:34:46 +02:00
|
|
|
|
2007-01-24 19:45:13 +01:00
|
|
|
if (NegFrameSize) {
|
|
|
|
// Show update of SP.
|
|
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
|
|
|
|
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
|
|
|
|
} else {
|
|
|
|
MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
|
|
|
|
Moves.push_back(MachineMove(FrameLabelId, SP, SP));
|
|
|
|
}
|
2006-08-25 21:40:59 +02:00
|
|
|
|
2007-01-24 19:45:13 +01:00
|
|
|
if (HasFP) {
|
|
|
|
MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
|
|
|
|
MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
|
|
|
|
Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
|
|
|
|
}
|
2006-08-29 18:24:26 +02:00
|
|
|
|
|
|
|
// Add callee saved registers to move list.
|
|
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
|
|
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
|
2007-01-24 19:45:13 +01:00
|
|
|
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
|
|
|
|
unsigned Reg = CSI[I].getReg();
|
|
|
|
if (Reg == PPC::LR || Reg == PPC::LR8) continue;
|
|
|
|
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
|
|
|
|
MachineLocation CSSrc(Reg);
|
|
|
|
Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
|
2006-08-29 18:24:26 +02:00
|
|
|
}
|
2007-01-24 19:45:13 +01:00
|
|
|
|
2007-02-01 17:31:34 +01:00
|
|
|
MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
|
|
|
|
MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
|
|
|
|
Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
|
|
|
|
|
2007-01-24 19:45:13 +01:00
|
|
|
// Mark effective beginning of when frame pointer is ready.
|
2007-01-26 22:22:28 +01:00
|
|
|
unsigned ReadyLabelId = MMI->NextLabelID();
|
2008-01-31 10:59:15 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
|
2007-01-24 19:45:13 +01:00
|
|
|
|
|
|
|
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
|
|
|
|
(IsPPC64 ? PPC::X1 : PPC::R1));
|
|
|
|
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
|
|
|
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
|
2006-04-07 18:34:46 +02:00
|
|
|
}
|
2006-11-16 23:43:37 +01:00
|
|
|
|
|
|
|
// If there is a frame pointer, copy R1 into R31
|
2006-04-04 00:03:29 +02:00
|
|
|
if (HasFP) {
|
2006-12-06 18:42:06 +01:00
|
|
|
if (!IsPPC64) {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::OR), PPC::R31)
|
|
|
|
.addReg(PPC::R1)
|
2006-11-28 00:37:22 +01:00
|
|
|
.addReg(PPC::R1);
|
2006-11-11 20:05:28 +01:00
|
|
|
} else {
|
2008-03-03 23:19:16 +01:00
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::OR8), PPC::X31)
|
|
|
|
.addReg(PPC::X1)
|
2006-11-28 00:37:22 +01:00
|
|
|
.addReg(PPC::X1);
|
2006-11-11 20:05:28 +01:00
|
|
|
}
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2005-10-16 07:39:50 +02:00
|
|
|
void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
|
|
|
|
MachineBasicBlock &MBB) const {
|
2004-08-17 06:55:41 +02:00
|
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
2006-01-09 19:28:21 +01:00
|
|
|
assert(MBBI->getOpcode() == PPC::BLR &&
|
2004-08-17 06:55:41 +02:00
|
|
|
"Can only insert epilog into returning blocks");
|
2005-04-22 01:30:14 +02:00
|
|
|
|
2006-04-11 21:29:21 +02:00
|
|
|
// Get alignment info so we know how to restore r1
|
|
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
2006-11-16 23:43:37 +01:00
|
|
|
unsigned MaxAlign = MFI->getMaxAlignment();
|
2006-04-11 21:29:21 +02:00
|
|
|
|
2006-01-12 00:03:54 +01:00
|
|
|
// Get the number of bytes allocated from the FrameInfo.
|
2006-11-16 23:43:37 +01:00
|
|
|
unsigned FrameSize = MFI->getStackSize();
|
2004-08-17 06:55:41 +02:00
|
|
|
|
2006-12-06 18:42:06 +01:00
|
|
|
// Get processor type.
|
|
|
|
bool IsPPC64 = Subtarget.isPPC64();
|
2007-02-25 06:34:32 +01:00
|
|
|
// Get operating system
|
|
|
|
bool IsMachoABI = Subtarget.isMachoABI();
|
2006-12-06 18:42:06 +01:00
|
|
|
// Check if the link register (LR) has been used.
|
2007-12-08 07:39:11 +01:00
|
|
|
bool UsesLR = MustSaveLR(MF);
|
2006-12-06 18:42:06 +01:00
|
|
|
// Do we have a frame pointer for this function?
|
2007-02-27 12:55:45 +01:00
|
|
|
bool HasFP = hasFP(MF) && FrameSize;
|
2007-02-25 06:34:32 +01:00
|
|
|
|
|
|
|
int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, IsMachoABI);
|
|
|
|
int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, IsMachoABI);
|
|
|
|
|
2007-02-27 12:55:45 +01:00
|
|
|
if (FrameSize) {
|
|
|
|
// The loaded (or persistent) stack pointer value is offset by the 'stwu'
|
|
|
|
// on entry to the function. Add this offset back now.
|
|
|
|
if (!Subtarget.isPPC64()) {
|
2008-03-10 23:59:46 +01:00
|
|
|
if (isInt16(FrameSize) && (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
|
2007-02-27 12:55:45 +01:00
|
|
|
!MFI->hasVarSizedObjects()) {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::ADDI), PPC::R1)
|
|
|
|
.addReg(PPC::R1).addImm(FrameSize);
|
|
|
|
} else {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LWZ),PPC::R1).addImm(0).addReg(PPC::R1);
|
|
|
|
}
|
2006-12-06 18:42:06 +01:00
|
|
|
} else {
|
2007-02-27 12:55:45 +01:00
|
|
|
if (isInt16(FrameSize) && TargetAlign >= MaxAlign &&
|
|
|
|
!MFI->hasVarSizedObjects()) {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::ADDI8), PPC::X1)
|
|
|
|
.addReg(PPC::X1).addImm(FrameSize);
|
|
|
|
} else {
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X1).addImm(0).addReg(PPC::X1);
|
|
|
|
}
|
2006-11-16 23:43:37 +01:00
|
|
|
}
|
2006-12-06 18:42:06 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (IsPPC64) {
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X0)
|
|
|
|
.addImm(LROffset/4).addReg(PPC::X1);
|
|
|
|
|
|
|
|
if (HasFP)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LD), PPC::X31)
|
|
|
|
.addImm(FPOffset/4).addReg(PPC::X1);
|
|
|
|
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::MTLR8)).addReg(PPC::X0);
|
|
|
|
} else {
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R0)
|
|
|
|
.addImm(LROffset).addReg(PPC::R1);
|
|
|
|
|
|
|
|
if (HasFP)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::LWZ), PPC::R31)
|
|
|
|
.addImm(FPOffset).addReg(PPC::R1);
|
|
|
|
|
|
|
|
if (UsesLR)
|
|
|
|
BuildMI(MBB, MBBI, TII.get(PPC::MTLR)).addReg(PPC::R0);
|
2004-08-17 06:55:41 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-04-07 18:34:46 +02:00
|
|
|
unsigned PPCRegisterInfo::getRARegister() const {
|
2006-11-14 19:44:47 +01:00
|
|
|
return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
|
2006-04-07 18:34:46 +02:00
|
|
|
}
|
|
|
|
|
2006-03-28 15:48:33 +02:00
|
|
|
unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
|
2006-11-11 20:05:28 +01:00
|
|
|
if (!Subtarget.isPPC64())
|
|
|
|
return hasFP(MF) ? PPC::R31 : PPC::R1;
|
|
|
|
else
|
|
|
|
return hasFP(MF) ? PPC::X31 : PPC::X1;
|
2006-04-07 18:34:46 +02:00
|
|
|
}
|
|
|
|
|
2007-01-24 19:45:13 +01:00
|
|
|
void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
|
2006-04-07 18:34:46 +02:00
|
|
|
const {
|
2006-08-25 21:40:59 +02:00
|
|
|
// Initial state of the frame pointer is R1.
|
2006-04-07 18:34:46 +02:00
|
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
|
|
MachineLocation Src(PPC::R1, 0);
|
2007-01-24 19:45:13 +01:00
|
|
|
Moves.push_back(MachineMove(0, Dst, Src));
|
2006-03-23 19:12:57 +01:00
|
|
|
}
|
|
|
|
|
2007-02-21 23:54:50 +01:00
|
|
|
unsigned PPCRegisterInfo::getEHExceptionRegister() const {
|
|
|
|
return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned PPCRegisterInfo::getEHHandlerRegister() const {
|
|
|
|
return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
|
|
|
|
}
|
|
|
|
|
2007-11-13 20:13:01 +01:00
|
|
|
int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
2007-11-13 00:36:13 +01:00
|
|
|
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
|
|
|
|
return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
|
2007-11-11 20:50:10 +01:00
|
|
|
}
|
|
|
|
|
2005-10-15 01:37:35 +02:00
|
|
|
#include "PPCGenRegisterInfo.inc"
|
2004-08-17 06:55:41 +02:00
|
|
|
|