RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 04:52:54 +02:00
Code Issues Projects Releases Wiki Activity
7e100ec90e
llvm-mirror/test/CodeGen/AArch64/arm64-fast-isel-rem.ll

44 lines
1.1 KiB
LLVM
Raw Normal View History

[AArch64][GlobalISel] Enable GlobalISel at -O0 by default Tests updated to explicitly use fast-isel at -O0 instead of implicitly. This change also allows an explicit -fast-isel option to override an implicitly enabled global-isel. Otherwise -fast-isel would have no effect at -O0. Differential Revision: https://reviews.llvm.org/D41362 llvm-svn: 321655
2018-01-02 17:30:47 +01:00
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
; CHECK-SSA-LABEL: Machine code for function t1
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. Work towards the unification of MIR and debug output by refactoring the interfaces. For MachineOperand::print, keep a simple version that can be easily called from `dump()`, and a more complex one which will be called from both the MIRPrinter and MachineInstr::print. Add extra checks inside MachineOperand for detached operands (operands with getParent() == nullptr). https://reviews.llvm.org/D40836 * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+)<def> ([^ ]+)/kill: \1 def \2 \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/kill: def ([^ ]+) ([^ ]+) ([^ ]+)<def>/kill: def \1 \2 def \3/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/<def>//g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<kill>/killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use,kill>/implicit killed \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<def[ ]*,[ ]*dead>/dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def[ ]*,[ ]*dead>/implicit-def dead \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-def>/implicit-def \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<imp-use>/implicit \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<internal>/internal \1/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" -o -name "*.s" \) -type f -print0 | xargs -0 sed -i '' -E 's/([^ ]+)<undef>/undef \1/g' llvm-svn: 320022
2017-12-07 11:40:31 +01:00
; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr
; CHECK-SSA-NOT: [[QUOTREG]] =
; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]]
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; CHECK-SSA-LABEL: Machine code for function t2
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
define i32 @t1(i32 %a, i32 %b) {
; CHECK: @t1
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
; CHECK: msub w0, [[TMP]], w1, w0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%1 = srem i32 %a, %b
ret i32 %1
}
define i64 @t2(i64 %a, i64 %b) {
; CHECK: @t2
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
; CHECK: msub x0, [[TMP]], x1, x0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%1 = srem i64 %a, %b
ret i64 %1
}
define i32 @t3(i32 %a, i32 %b) {
; CHECK: @t3
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
; CHECK: msub w0, [[TMP]], w1, w0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%1 = urem i32 %a, %b
ret i32 %1
}
define i64 @t4(i64 %a, i64 %b) {
; CHECK: @t4
ARM64: make sure FastISel emits SSA MachineInstrs We need to use a temporary register for a 2-step operation like REM. llvm-svn: 208297
2014-05-08 12:30:56 +02:00
; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
; CHECK: msub x0, [[TMP]], x1, x0
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 11:18:08 +01:00
%1 = urem i64 %a, %b
ret i64 %1
}
Reference in New Issue Copy Permalink