2016-11-02 00:40:28 +01:00
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//===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2016-11-02 00:40:28 +01:00
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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2017-10-19 16:29:03 +02:00
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// Declarations that describe the RISC-V register files
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2016-11-02 00:40:28 +01:00
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//===----------------------------------------------------------------------===//
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let Namespace = "RISCV" in {
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2017-10-19 16:29:03 +02:00
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class RISCVReg<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
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let HWEncoding{4-0} = Enc;
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let AltNames = alt;
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2016-11-02 00:40:28 +01:00
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}
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2017-12-07 11:26:05 +01:00
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class RISCVReg32<bits<5> Enc, string n, list<string> alt = []> : Register<n> {
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let HWEncoding{4-0} = Enc;
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let AltNames = alt;
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}
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2017-12-07 11:46:23 +01:00
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// Because RISCVReg64 register have AsmName and AltNames that alias with their
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// 32-bit sub-register, RISCVAsmParser will need to coerce a register number
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// from a RISCVReg32 to the equivalent RISCVReg64 when appropriate.
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def sub_32 : SubRegIndex<32>;
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class RISCVReg64<RISCVReg32 subreg> : Register<""> {
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let HWEncoding{4-0} = subreg.HWEncoding{4-0};
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let SubRegs = [subreg];
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let SubRegIndices = [sub_32];
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let AsmName = subreg.AsmName;
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let AltNames = subreg.AltNames;
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}
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2019-10-24 06:29:28 +02:00
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class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
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list<string> alt = []>
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: RegisterWithSubRegs<n, subregs> {
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let HWEncoding{4-0} = Enc;
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let AltNames = alt;
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}
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2017-10-19 16:29:03 +02:00
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def ABIRegAltName : RegAltNameIndex;
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2019-10-24 06:29:28 +02:00
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def sub_vrm2 : SubRegIndex<64, -1>;
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def sub_vrm2_hi : SubRegIndex<64, -1>;
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def sub_vrm4 : SubRegIndex<128, -1>;
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def sub_vrm4_hi : SubRegIndex<128, -1>;
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def sub_vrm8 : SubRegIndex<256, -1>;
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def sub_vrm8_hi : SubRegIndex<256, -1>;
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2017-10-19 16:29:03 +02:00
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} // Namespace = "RISCV"
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2016-11-02 00:40:28 +01:00
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// Integer registers
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[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
llvm-svn: 333132
2018-05-23 23:34:30 +02:00
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// CostPerUse is set higher for registers that may not be compressible as they
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// are not part of GPRC, the most restrictive register class used by the
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// compressed instruction set. This will influence the greedy register
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// allocator to reduce the use of registers that can't be encoded in 16 bit
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// instructions. This affects register allocation even when compressed
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// instruction isn't targeted, we see no major negative codegen impact.
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2016-11-02 00:40:28 +01:00
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let RegAltNameIndices = [ABIRegAltName] in {
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2017-10-19 16:29:03 +02:00
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def X0 : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
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[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
llvm-svn: 333132
2018-05-23 23:34:30 +02:00
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let CostPerUse = 1 in {
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2017-10-19 16:29:03 +02:00
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def X1 : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
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def X2 : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
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def X3 : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
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def X4 : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
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def X5 : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
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def X6 : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
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def X7 : RISCVReg<7, "x7", ["t2"]>, DwarfRegNum<[7]>;
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[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
llvm-svn: 333132
2018-05-23 23:34:30 +02:00
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}
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2019-03-11 22:35:26 +01:00
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def X8 : RISCVReg<8, "x8", ["s0", "fp"]>, DwarfRegNum<[8]>;
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2017-10-19 16:29:03 +02:00
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def X9 : RISCVReg<9, "x9", ["s1"]>, DwarfRegNum<[9]>;
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def X10 : RISCVReg<10,"x10", ["a0"]>, DwarfRegNum<[10]>;
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def X11 : RISCVReg<11,"x11", ["a1"]>, DwarfRegNum<[11]>;
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def X12 : RISCVReg<12,"x12", ["a2"]>, DwarfRegNum<[12]>;
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def X13 : RISCVReg<13,"x13", ["a3"]>, DwarfRegNum<[13]>;
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def X14 : RISCVReg<14,"x14", ["a4"]>, DwarfRegNum<[14]>;
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def X15 : RISCVReg<15,"x15", ["a5"]>, DwarfRegNum<[15]>;
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[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
llvm-svn: 333132
2018-05-23 23:34:30 +02:00
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let CostPerUse = 1 in {
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2017-10-19 16:29:03 +02:00
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def X16 : RISCVReg<16,"x16", ["a6"]>, DwarfRegNum<[16]>;
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def X17 : RISCVReg<17,"x17", ["a7"]>, DwarfRegNum<[17]>;
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def X18 : RISCVReg<18,"x18", ["s2"]>, DwarfRegNum<[18]>;
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def X19 : RISCVReg<19,"x19", ["s3"]>, DwarfRegNum<[19]>;
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def X20 : RISCVReg<20,"x20", ["s4"]>, DwarfRegNum<[20]>;
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def X21 : RISCVReg<21,"x21", ["s5"]>, DwarfRegNum<[21]>;
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def X22 : RISCVReg<22,"x22", ["s6"]>, DwarfRegNum<[22]>;
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def X23 : RISCVReg<23,"x23", ["s7"]>, DwarfRegNum<[23]>;
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def X24 : RISCVReg<24,"x24", ["s8"]>, DwarfRegNum<[24]>;
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def X25 : RISCVReg<25,"x25", ["s9"]>, DwarfRegNum<[25]>;
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def X26 : RISCVReg<26,"x26", ["s10"]>, DwarfRegNum<[26]>;
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def X27 : RISCVReg<27,"x27", ["s11"]>, DwarfRegNum<[27]>;
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def X28 : RISCVReg<28,"x28", ["t3"]>, DwarfRegNum<[28]>;
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def X29 : RISCVReg<29,"x29", ["t4"]>, DwarfRegNum<[29]>;
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def X30 : RISCVReg<30,"x30", ["t5"]>, DwarfRegNum<[30]>;
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def X31 : RISCVReg<31,"x31", ["t6"]>, DwarfRegNum<[31]>;
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[RISCV] Set CostPerUse for registers
Summary:
Set CostPerUse higher for registers that are not used in the compressed
instruction set. This will influence the greedy register allocator to reduce
the use of registers that can't be encoded in 16 bit instructions. This
affects register allocation even when compressed instruction isn't targeted,
we see no major negative codegen impact.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang
Differential Revision: https://reviews.llvm.org/D47039
llvm-svn: 333132
2018-05-23 23:34:30 +02:00
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}
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2016-11-02 00:40:28 +01:00
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}
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2017-10-19 16:29:03 +02:00
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def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
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[i32, i64, i32]>;
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2016-11-02 00:40:28 +01:00
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2017-10-19 23:37:38 +02:00
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// The order of registers represents the preferred allocation sequence.
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// Registers are listed in the order caller-save, callee-save, specials.
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def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 10, 17),
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(sequence "X%u", 5, 7),
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(sequence "X%u", 28, 31),
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(sequence "X%u", 8, 9),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 0, 4)
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2017-10-19 16:29:03 +02:00
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)> {
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2017-12-07 13:50:32 +01:00
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2019-08-21 16:00:58 +02:00
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def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2017-12-07 13:50:32 +01:00
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// The order of registers represents the preferred allocation sequence.
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// Registers are listed in the order caller-save, callee-save, specials.
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def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 10, 17),
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(sequence "X%u", 5, 7),
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(sequence "X%u", 28, 31),
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(sequence "X%u", 8, 9),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 1, 4)
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)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2017-12-13 10:32:55 +01:00
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def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 10, 17),
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(sequence "X%u", 5, 7),
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(sequence "X%u", 28, 31),
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(sequence "X%u", 8, 9),
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(sequence "X%u", 18, 27),
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X1, X3, X4
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)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2017-12-07 13:50:32 +01:00
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def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 10, 15),
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(sequence "X%u", 8, 9)
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)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2018-05-24 00:44:08 +02:00
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// For indirect tail calls, we can't use callee-saved registers, as they are
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// restored to the saved value before the tail call, which would clobber a call
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// address.
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def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 5, 7),
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(sequence "X%u", 10, 17),
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(sequence "X%u", 28, 31)
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)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2017-12-07 13:50:32 +01:00
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def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
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2017-10-19 16:29:03 +02:00
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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2017-12-07 11:26:05 +01:00
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// Floating point registers
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let RegAltNameIndices = [ABIRegAltName] in {
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2019-09-27 17:49:10 +02:00
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def F0_F : RISCVReg32<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
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def F1_F : RISCVReg32<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
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def F2_F : RISCVReg32<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
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def F3_F : RISCVReg32<3, "f3", ["ft3"]>, DwarfRegNum<[35]>;
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def F4_F : RISCVReg32<4, "f4", ["ft4"]>, DwarfRegNum<[36]>;
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def F5_F : RISCVReg32<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
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def F6_F : RISCVReg32<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
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def F7_F : RISCVReg32<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
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def F8_F : RISCVReg32<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
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def F9_F : RISCVReg32<9, "f9", ["fs1"]>, DwarfRegNum<[41]>;
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def F10_F : RISCVReg32<10,"f10", ["fa0"]>, DwarfRegNum<[42]>;
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def F11_F : RISCVReg32<11,"f11", ["fa1"]>, DwarfRegNum<[43]>;
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def F12_F : RISCVReg32<12,"f12", ["fa2"]>, DwarfRegNum<[44]>;
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def F13_F : RISCVReg32<13,"f13", ["fa3"]>, DwarfRegNum<[45]>;
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def F14_F : RISCVReg32<14,"f14", ["fa4"]>, DwarfRegNum<[46]>;
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def F15_F : RISCVReg32<15,"f15", ["fa5"]>, DwarfRegNum<[47]>;
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def F16_F : RISCVReg32<16,"f16", ["fa6"]>, DwarfRegNum<[48]>;
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def F17_F : RISCVReg32<17,"f17", ["fa7"]>, DwarfRegNum<[49]>;
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def F18_F : RISCVReg32<18,"f18", ["fs2"]>, DwarfRegNum<[50]>;
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def F19_F : RISCVReg32<19,"f19", ["fs3"]>, DwarfRegNum<[51]>;
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def F20_F : RISCVReg32<20,"f20", ["fs4"]>, DwarfRegNum<[52]>;
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def F21_F : RISCVReg32<21,"f21", ["fs5"]>, DwarfRegNum<[53]>;
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def F22_F : RISCVReg32<22,"f22", ["fs6"]>, DwarfRegNum<[54]>;
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def F23_F : RISCVReg32<23,"f23", ["fs7"]>, DwarfRegNum<[55]>;
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def F24_F : RISCVReg32<24,"f24", ["fs8"]>, DwarfRegNum<[56]>;
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def F25_F : RISCVReg32<25,"f25", ["fs9"]>, DwarfRegNum<[57]>;
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def F26_F : RISCVReg32<26,"f26", ["fs10"]>, DwarfRegNum<[58]>;
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def F27_F : RISCVReg32<27,"f27", ["fs11"]>, DwarfRegNum<[59]>;
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def F28_F : RISCVReg32<28,"f28", ["ft8"]>, DwarfRegNum<[60]>;
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def F29_F : RISCVReg32<29,"f29", ["ft9"]>, DwarfRegNum<[61]>;
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def F30_F : RISCVReg32<30,"f30", ["ft10"]>, DwarfRegNum<[62]>;
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def F31_F : RISCVReg32<31,"f31", ["ft11"]>, DwarfRegNum<[63]>;
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2017-12-07 11:46:23 +01:00
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foreach Index = 0-31 in {
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2019-09-27 17:49:10 +02:00
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def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
|
2017-12-07 11:46:23 +01:00
|
|
|
DwarfRegNum<[!add(Index, 32)]>;
|
|
|
|
}
|
2017-12-07 11:26:05 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
// The order of registers represents the preferred allocation sequence,
|
|
|
|
// meaning caller-save regs are listed before callee-save.
|
|
|
|
def FPR32 : RegisterClass<"RISCV", [f32], 32, (add
|
2019-09-27 17:49:10 +02:00
|
|
|
(sequence "F%u_F", 0, 7),
|
|
|
|
(sequence "F%u_F", 10, 17),
|
|
|
|
(sequence "F%u_F", 28, 31),
|
|
|
|
(sequence "F%u_F", 8, 9),
|
|
|
|
(sequence "F%u_F", 18, 27)
|
2017-12-07 11:26:05 +01:00
|
|
|
)>;
|
2017-12-07 11:46:23 +01:00
|
|
|
|
2017-12-13 10:32:55 +01:00
|
|
|
def FPR32C : RegisterClass<"RISCV", [f32], 32, (add
|
2019-09-27 17:49:10 +02:00
|
|
|
(sequence "F%u_F", 10, 15),
|
|
|
|
(sequence "F%u_F", 8, 9)
|
2017-12-13 10:32:55 +01:00
|
|
|
)>;
|
|
|
|
|
2017-12-07 11:46:23 +01:00
|
|
|
// The order of registers represents the preferred allocation sequence,
|
|
|
|
// meaning caller-save regs are listed before callee-save.
|
|
|
|
def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
|
2019-09-27 17:49:10 +02:00
|
|
|
(sequence "F%u_D", 0, 7),
|
|
|
|
(sequence "F%u_D", 10, 17),
|
|
|
|
(sequence "F%u_D", 28, 31),
|
|
|
|
(sequence "F%u_D", 8, 9),
|
|
|
|
(sequence "F%u_D", 18, 27)
|
2017-12-07 11:46:23 +01:00
|
|
|
)>;
|
2017-12-13 10:32:55 +01:00
|
|
|
|
|
|
|
def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
|
2019-09-27 17:49:10 +02:00
|
|
|
(sequence "F%u_D", 10, 15),
|
|
|
|
(sequence "F%u_D", 8, 9)
|
2017-12-13 10:32:55 +01:00
|
|
|
)>;
|
2019-10-24 06:29:28 +02:00
|
|
|
|
|
|
|
// Vector registers
|
|
|
|
let RegAltNameIndices = [ABIRegAltName] in {
|
|
|
|
foreach Index = 0-31 in {
|
|
|
|
def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
|
|
|
|
24, 26, 28, 30] in {
|
|
|
|
def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
|
|
|
|
[!cast<Register>("V"#Index),
|
|
|
|
!cast<Register>("V"#!add(Index, 1))],
|
|
|
|
["v"#Index]>,
|
|
|
|
DwarfRegAlias<!cast<Register>("V"#Index)> {
|
|
|
|
let SubRegIndices = [sub_vrm2, sub_vrm2_hi];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
|
|
|
|
def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
|
|
|
|
[!cast<Register>("V"#Index#"M2"),
|
|
|
|
!cast<Register>("V"#!add(Index, 2)#"M2")],
|
|
|
|
["v"#Index]>,
|
|
|
|
DwarfRegAlias<!cast<Register>("V"#Index)> {
|
|
|
|
let SubRegIndices = [sub_vrm4, sub_vrm4_hi];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
foreach Index = [0, 8, 16, 24] in {
|
|
|
|
def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
|
|
|
|
[!cast<Register>("V"#Index#"M4"),
|
|
|
|
!cast<Register>("V"#!add(Index, 4)#"M4")],
|
|
|
|
["v"#Index]>,
|
|
|
|
DwarfRegAlias<!cast<Register>("V"#Index)> {
|
|
|
|
let SubRegIndices = [sub_vrm8, sub_vrm8_hi];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;
|
|
|
|
def VL : RISCVReg<0, "vl", ["vl"]>;
|
|
|
|
}
|
|
|
|
|
|
|
|
class RegisterTypes<list<ValueType> reg_types> {
|
|
|
|
list<ValueType> types = reg_types;
|
|
|
|
}
|
|
|
|
|
|
|
|
// The order of registers represents the preferred allocation sequence,
|
|
|
|
// meaning caller-save regs are listed before callee-save.
|
|
|
|
def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
|
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
Implement vmsge{u}.vx pseudo instruction.
According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.
unmasked va >= x
pseudoinstruction: vmsge{u}.vx vd, va, x
expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
masked va >= x, vd != v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
masked va >= x, vd == v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt
Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.
Differential Revision: https://reviews.llvm.org/D84732
2020-07-28 08:45:28 +02:00
|
|
|
64, (add
|
2019-10-24 06:29:28 +02:00
|
|
|
(sequence "V%u", 25, 31),
|
|
|
|
(sequence "V%u", 8, 24),
|
|
|
|
(sequence "V%u", 0, 7)
|
|
|
|
)> {
|
|
|
|
let Size = 64;
|
|
|
|
}
|
|
|
|
|
[RISCV] Support vmsge.vx and vmsgeu.vx pseudo instructions in RVV.
Implement vmsge{u}.vx pseudo instruction.
According to RISC-V V specification, there are different scenarios for this
pseudo instruction. I list them below.
unmasked va >= x
pseudoinstruction: vmsge{u}.vx vd, va, x
expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
masked va >= x, vd != v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
masked va >= x, vd == v0
pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
expansion: vmslt{u}.vx vt, va, x; vmandnot.mm vd, vd, vt
Use pseudo instruction to model vmsge{u}.vx. The pseudo instruction will convert
to different expansion according to the condition.
Differential Revision: https://reviews.llvm.org/D84732
2020-07-28 08:45:28 +02:00
|
|
|
def VRNoV0 : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
|
|
|
|
64, (add
|
|
|
|
(sequence "V%u", 25, 31),
|
|
|
|
(sequence "V%u", 8, 24),
|
|
|
|
(sequence "V%u", 1, 7)
|
|
|
|
)> {
|
|
|
|
let Size = 64;
|
|
|
|
}
|
|
|
|
|
2019-10-24 06:29:28 +02:00
|
|
|
def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64,
|
|
|
|
(add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
|
|
|
|
V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> {
|
|
|
|
let Size = 128;
|
|
|
|
}
|
|
|
|
|
|
|
|
def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64,
|
|
|
|
(add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> {
|
|
|
|
let Size = 256;
|
|
|
|
}
|
|
|
|
|
|
|
|
def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64,
|
|
|
|
(add V8M8, V16M8, V24M8, V0M8)> {
|
|
|
|
let Size = 512;
|
|
|
|
}
|
|
|
|
|
|
|
|
def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>;
|
|
|
|
|
|
|
|
def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add
|
|
|
|
(sequence "V%u", 25, 31),
|
|
|
|
(sequence "V%u", 8, 24),
|
|
|
|
(sequence "V%u", 0, 7))> {
|
|
|
|
let Size = 64;
|
|
|
|
}
|
|
|
|
|
|
|
|
def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> {
|
|
|
|
let Size = 64;
|
|
|
|
}
|