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llvm-mirror/test/CodeGen/X86/load-partial.ll

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[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
[X86][SSE] Add partial dereferenceable vector load test inspired by PR21780 llvm-svn: 365145
2019-07-04 17:00:04 +02:00
;
; Partial Vector Loads - PR16739
;
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
define <4 x float> @load_float4_float3(<4 x float>* nocapture readonly dereferenceable(16)) {
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
2019-07-10 12:46:36 +02:00
; SSE-LABEL: load_float4_float3:
; SSE: # %bb.0:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: retq
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
;
; AVX-LABEL: load_float4_float3:
; AVX: # %bb.0:
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
2019-07-10 12:46:36 +02:00
; AVX-NEXT: vmovups (%rdi), %xmm0
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
; AVX-NEXT: retq
%p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
%p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
%p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%ld0 = load float, float* %p0, align 4
%ld1 = load float, float* %p1, align 4
%ld2 = load float, float* %p2, align 4
%r0 = insertelement <4 x float> undef, float %ld0, i32 0
%r1 = insertelement <4 x float> %r0, float %ld1, i32 1
%r2 = insertelement <4 x float> %r1, float %ld2, i32 2
ret <4 x float> %r2
}
[X86][SSE] Add shuffled load tests from PR16739 llvm-svn: 369116
2019-08-16 16:47:59 +02:00
define <4 x float> @load_float4_float3_0122(<4 x float>* nocapture readonly dereferenceable(16)) {
; SSE-LABEL: load_float4_float3_0122:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: load_float4_float3_0122:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vmovups (%rdi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]
; AVX-NEXT: retq
%p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
%p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
%p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%ld0 = load float, float* %p0, align 4
%ld1 = load float, float* %p1, align 4
%ld2 = load float, float* %p2, align 4
%r0 = insertelement <4 x float> undef, float %ld0, i32 0
%r1 = insertelement <4 x float> %r0, float %ld1, i32 1
%r2 = insertelement <4 x float> %r1, float %ld2, i32 2
%r3 = insertelement <4 x float> %r2, float %ld2, i32 3
ret <4 x float> %r3
}
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
define <8 x float> @load_float8_float3(<4 x float>* nocapture readonly dereferenceable(16)) {
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
2019-07-10 12:46:36 +02:00
; SSE-LABEL: load_float8_float3:
; SSE: # %bb.0:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: retq
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
;
; AVX-LABEL: load_float8_float3:
; AVX: # %bb.0:
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
2019-07-10 12:46:36 +02:00
; AVX-NEXT: vmovups (%rdi), %xmm0
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
; AVX-NEXT: retq
%p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
%p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
%p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%ld0 = load float, float* %p0, align 4
%ld1 = load float, float* %p1, align 4
%ld2 = load float, float* %p2, align 4
%r0 = insertelement <8 x float> undef, float %ld0, i32 0
%r1 = insertelement <8 x float> %r0, float %ld1, i32 1
%r2 = insertelement <8 x float> %r1, float %ld2, i32 2
ret <8 x float> %r2
}
[X86][SSE] Add shuffled load tests from PR16739 llvm-svn: 369116
2019-08-16 16:47:59 +02:00
define <8 x float> @load_float8_float3_0122(<4 x float>* nocapture readonly dereferenceable(16)) {
; SSE-LABEL: load_float8_float3_0122:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: load_float8_float3_0122:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vmovups (%rdi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]
; AVX-NEXT: retq
%p0 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 0
%p1 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 1
%p2 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%ld0 = load float, float* %p0, align 4
%ld1 = load float, float* %p1, align 4
%ld2 = load float, float* %p2, align 4
%r0 = insertelement <8 x float> undef, float %ld0, i32 0
%r1 = insertelement <8 x float> %r0, float %ld1, i32 1
%r2 = insertelement <8 x float> %r1, float %ld2, i32 2
%r3 = insertelement <8 x float> %r2, float %ld2, i32 3
ret <8 x float> %r3
}
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
define <4 x float> @load_float4_float3_as_float2_float(<4 x float>* nocapture readonly dereferenceable(16)) {
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED) This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load. A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match. Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle. Fixed out of bounds load assert identified in rL366501 Differential Revision: https://reviews.llvm.org/D64551 llvm-svn: 366681
2019-07-22 14:44:10 +02:00
; SSE-LABEL: load_float4_float3_as_float2_float:
; SSE: # %bb.0:
; SSE-NEXT: movups (%rdi), %xmm0
; SSE-NEXT: retq
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
;
; AVX-LABEL: load_float4_float3_as_float2_float:
; AVX: # %bb.0:
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED) This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load. A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match. Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle. Fixed out of bounds load assert identified in rL366501 Differential Revision: https://reviews.llvm.org/D64551 llvm-svn: 366681
2019-07-22 14:44:10 +02:00
; AVX-NEXT: vmovups (%rdi), %xmm0
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to <2 x float>*
%3 = load <2 x float>, <2 x float>* %2, align 4
%4 = extractelement <2 x float> %3, i32 0
%5 = insertelement <4 x float> undef, float %4, i32 0
%6 = extractelement <2 x float> %3, i32 1
%7 = insertelement <4 x float> %5, float %6, i32 1
%8 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%9 = load float, float* %8, align 4
%10 = insertelement <4 x float> %7, float %9, i32 2
ret <4 x float> %10
}
[X86][SSE] Add shuffled load tests from PR16739 llvm-svn: 369116
2019-08-16 16:47:59 +02:00
define <4 x float> @load_float4_float3_as_float2_float_0122(<4 x float>* nocapture readonly dereferenceable(16)) {
; SSE-LABEL: load_float4_float3_as_float2_float_0122:
; SSE: # %bb.0:
; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: load_float4_float3_as_float2_float_0122:
; AVX: # %bb.0:
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0]
; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to <2 x float>*
%3 = load <2 x float>, <2 x float>* %2, align 4
%4 = extractelement <2 x float> %3, i32 0
%5 = insertelement <4 x float> undef, float %4, i32 0
%6 = extractelement <2 x float> %3, i32 1
%7 = insertelement <4 x float> %5, float %6, i32 1
%8 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%9 = load float, float* %8, align 4
%10 = insertelement <4 x float> %7, float %9, i32 2
%11 = insertelement <4 x float> %10, float %9, i32 3
ret <4 x float> %11
}
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
define <4 x float> @load_float4_float3_trunc(<4 x float>* nocapture readonly dereferenceable(16)) {
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED) This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load. A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match. Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle. Fixed out of bounds load assert identified in rL366501 Differential Revision: https://reviews.llvm.org/D64551 llvm-svn: 366681
2019-07-22 14:44:10 +02:00
; SSE-LABEL: load_float4_float3_trunc:
; SSE: # %bb.0:
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: retq
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
;
; AVX-LABEL: load_float4_float3_trunc:
; AVX: # %bb.0:
[X86] EltsFromConsecutiveLoads - support common source loads (REAPPLIED) This patch enables us to find the source loads for each element, splitting them into a Load and ByteOffset, and attempts to recognise consecutive loads that are in fact from the same source load. A helper function, findEltLoadSrc, recurses to find a LoadSDNode and determines the element's byte offset within it. When attempting to match consecutive loads, byte offsetted loads then attempt to matched against a previous load that has already been confirmed to be a consecutive match. Next step towards PR16739 - after this we just need to account for shuffling/repeated elements to create a vector load + shuffle. Fixed out of bounds load assert identified in rL366501 Differential Revision: https://reviews.llvm.org/D64551 llvm-svn: 366681
2019-07-22 14:44:10 +02:00
; AVX-NEXT: vmovaps (%rdi), %xmm0
[X86][SSE] Add some partial dereferenceable vector load tests inspired by PR16739 llvm-svn: 365138
2019-07-04 15:31:49 +02:00
; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to i64*
%3 = load i64, i64* %2, align 16
%4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%5 = bitcast float* %4 to i64*
%6 = load i64, i64* %5, align 8
%7 = trunc i64 %3 to i32
%8 = bitcast i32 %7 to float
%9 = insertelement <4 x float> undef, float %8, i32 0
%10 = lshr i64 %3, 32
%11 = trunc i64 %10 to i32
%12 = bitcast i32 %11 to float
%13 = insertelement <4 x float> %9, float %12, i32 1
%14 = trunc i64 %6 to i32
%15 = bitcast i32 %14 to float
%16 = insertelement <4 x float> %13, float %15, i32 2
ret <4 x float> %16
}
[X86][SSE] Add partial dereferenceable vector load test inspired by PR21780 llvm-svn: 365145
2019-07-04 17:00:04 +02:00
[X86][SSE] Add shuffled load tests from PR16739 llvm-svn: 369116
2019-08-16 16:47:59 +02:00
define <4 x float> @load_float4_float3_trunc_0122(<4 x float>* nocapture readonly dereferenceable(16)) {
; SSE-LABEL: load_float4_float3_trunc_0122:
; SSE: # %bb.0:
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-NEXT: movaps (%rdi), %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: load_float4_float3_trunc_0122:
; AVX: # %bb.0:
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-NEXT: vmovaps (%rdi), %xmm1
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]
; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to i64*
%3 = load i64, i64* %2, align 16
%4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%5 = bitcast float* %4 to i64*
%6 = load i64, i64* %5, align 8
%7 = trunc i64 %3 to i32
%8 = bitcast i32 %7 to float
%9 = insertelement <4 x float> undef, float %8, i32 0
%10 = lshr i64 %3, 32
%11 = trunc i64 %10 to i32
%12 = bitcast i32 %11 to float
%13 = insertelement <4 x float> %9, float %12, i32 1
%14 = trunc i64 %6 to i32
%15 = bitcast i32 %14 to float
%16 = insertelement <4 x float> %13, float %15, i32 2
%17 = insertelement <4 x float> %16, float %15, i32 3
ret <4 x float> %17
}
define <4 x float> @load_float4_float3_trunc_0123(<4 x float>* nocapture readonly dereferenceable(16)) {
; SSE2-LABEL: load_float4_float3_trunc_0123:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps (%rdi), %xmm0
; SSE2-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_float4_float3_trunc_0123:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movaps (%rdi), %xmm0
; SSSE3-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_float4_float3_trunc_0123:
; SSE41: # %bb.0:
; SSE41-NEXT: movaps (%rdi), %xmm0
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; SSE41-NEXT: retq
;
; AVX-LABEL: load_float4_float3_trunc_0123:
; AVX: # %bb.0:
; AVX-NEXT: vmovaps (%rdi), %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-NEXT: retq
%2 = bitcast <4 x float>* %0 to i64*
%3 = load i64, i64* %2, align 16
%4 = getelementptr inbounds <4 x float>, <4 x float>* %0, i64 0, i64 2
%5 = bitcast float* %4 to i64*
%6 = load i64, i64* %5, align 8
%7 = trunc i64 %3 to i32
%8 = bitcast i32 %7 to float
%9 = insertelement <4 x float> undef, float %8, i32 0
%10 = lshr i64 %3, 32
%11 = trunc i64 %10 to i32
%12 = bitcast i32 %11 to float
%13 = insertelement <4 x float> %9, float %12, i32 1
%14 = trunc i64 %6 to i32
%15 = bitcast i32 %14 to float
%16 = insertelement <4 x float> %13, float %15, i32 2
%17 = lshr i64 %6, 32
%18 = trunc i64 %17 to i32
%19 = bitcast i32 %18 to float
%20 = insertelement <4 x float> %16, float %19, i32 3
ret <4 x float> %20
}
[X86][SSE] Add partial dereferenceable vector load test inspired by PR21780 llvm-svn: 365145
2019-07-04 17:00:04 +02:00
; PR21780
define <4 x double> @load_double4_0u2u(double* nocapture readonly dereferenceable(32)) {
; SSE2-LABEL: load_double4_0u2u:
; SSE2: # %bb.0:
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; SSE2-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0,0]
; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_double4_0u2u:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
; SSSE3-NEXT: movddup {{.*#+}} xmm1 = mem[0,0]
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_double4_0u2u:
; SSE41: # %bb.0:
; SSE41-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
; SSE41-NEXT: movddup {{.*#+}} xmm1 = mem[0,0]
; SSE41-NEXT: retq
;
; AVX-LABEL: load_double4_0u2u:
; AVX: # %bb.0:
[X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it. Another step towards partial vector loads...... Differential Revision: https://reviews.llvm.org/D64205 llvm-svn: 365614
2019-07-10 12:46:36 +02:00
; AVX-NEXT: vmovddup {{.*#+}} ymm0 = mem[0,0,2,2]
[X86][SSE] Add partial dereferenceable vector load test inspired by PR21780 llvm-svn: 365145
2019-07-04 17:00:04 +02:00
; AVX-NEXT: retq
%2 = load double, double* %0, align 8
%3 = insertelement <4 x double> undef, double %2, i32 0
%4 = getelementptr inbounds double, double* %0, i64 2
%5 = load double, double* %4, align 8
%6 = insertelement <4 x double> %3, double %5, i32 2
%7 = shufflevector <4 x double> %6, <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
ret <4 x double> %7
}
[X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501 Test case that led to rL366441 being reverted at rL366501 llvm-svn: 366678
2019-07-22 14:17:56 +02:00
; Test case identified in rL366501
@h = local_unnamed_addr global i8 0, align 1
define i32 @load_partial_illegal_type() {
; SSE2-LABEL: load_partial_illegal_type:
; SSE2: # %bb.0:
; SSE2-NEXT: movzwl {{.*}}(%rip), %eax
; SSE2-NEXT: movd %eax, %xmm0
[TargetLowering] SimplifyDemandedVectorElts - add DemandedElts mask to ISD::BITCAST SimplifyDemandedBits call. This fixes most of the regressions introduced in the rG4bc6f6332028 bugfix. The vector-trunc.ll issue should be fixed by D66004.
2020-03-10 14:38:33 +01:00
; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-NEXT: por {{.*}}(%rip), %xmm0
; SSE2-NEXT: movd %xmm0, %eax
[X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501 Test case that led to rL366441 being reverted at rL366501 llvm-svn: 366678
2019-07-22 14:17:56 +02:00
; SSE2-NEXT: retq
;
; SSSE3-LABEL: load_partial_illegal_type:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movzwl {{.*}}(%rip), %eax
; SSSE3-NEXT: movd %eax, %xmm0
[X86][SSE] Add SimplifyDemandedVectorEltsForTargetShuffle to handle target shuffle variable masks Pulled out from the ongoing work on D66004, currently we don't do a good job of simplifying variable shuffle masks that have already lowered to constant pool entries. This patch adds SimplifyDemandedVectorEltsForTargetShuffle (a custom x86 helper) to first try SimplifyDemandedVectorElts (which we already do) and then constant pool simplification to help mark undefined elements. To prevent lowering/combines infinite loops, we only handle basic constant pool loads instead of creating new BUILD_VECTOR nodes for lowering - e.g. we don't try to convert them to broadcast/vzext_load - there might be some benefit to this but if so I'd rather we come up with some way to reuse existing code than reimplement a lot of BUILD_VECTOR code. Differential Revision: https://reviews.llvm.org/D81791
2020-06-21 12:16:07 +02:00
; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1],zero,xmm0[3,u,u,u,u,u,u,u,u,u,u,u,u]
[TargetLowering] SimplifyDemandedVectorElts - add DemandedElts mask to ISD::BITCAST SimplifyDemandedBits call. This fixes most of the regressions introduced in the rG4bc6f6332028 bugfix. The vector-trunc.ll issue should be fixed by D66004.
2020-03-10 14:38:33 +01:00
; SSSE3-NEXT: por {{.*}}(%rip), %xmm0
[X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501 Test case that led to rL366441 being reverted at rL366501 llvm-svn: 366678
2019-07-22 14:17:56 +02:00
; SSSE3-NEXT: movd %xmm0, %eax
; SSSE3-NEXT: retq
;
; SSE41-LABEL: load_partial_illegal_type:
; SSE41: # %bb.0:
; SSE41-NEXT: movzwl {{.*}}(%rip), %eax
; SSE41-NEXT: movd %eax, %xmm0
; SSE41-NEXT: movl $2, %eax
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-07 18:24:26 +02:00
; SSE41-NEXT: pinsrb $2, %eax, %xmm0
[X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501 Test case that led to rL366441 being reverted at rL366501 llvm-svn: 366678
2019-07-22 14:17:56 +02:00
; SSE41-NEXT: movd %xmm0, %eax
; SSE41-NEXT: retq
;
; AVX-LABEL: load_partial_illegal_type:
; AVX: # %bb.0:
; AVX-NEXT: movzwl {{.*}}(%rip), %eax
; AVX-NEXT: vmovd %eax, %xmm0
; AVX-NEXT: movl $2, %eax
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default." The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
2019-08-07 18:24:26 +02:00
; AVX-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
[X86][SSE] Add EltsFromConsecutiveLoads test case identified in rL366501 Test case that led to rL366441 being reverted at rL366501 llvm-svn: 366678
2019-07-22 14:17:56 +02:00
; AVX-NEXT: vmovd %xmm0, %eax
; AVX-NEXT: retq
%1 = load <2 x i8>, <2 x i8>* bitcast (i8* @h to <2 x i8>*), align 1
%2 = shufflevector <2 x i8> %1, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%3 = insertelement <4 x i8> %2, i8 2, i32 2
%4 = bitcast <4 x i8> %3 to i32
ret i32 %4
}
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
define void @PR43227(i32* %explicit_0, <8 x i32>* %explicit_1) {
; SSE2-LABEL: PR43227:
; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast. getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements. I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.
2020-07-29 12:32:07 +02:00
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
; SSE2-NEXT: xorps %xmm1, %xmm1
; SSE2-NEXT: xorps %xmm2, %xmm2
; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSE2-NEXT: movaps %xmm1, 672(%rsi)
; SSE2-NEXT: movaps %xmm2, 688(%rsi)
; SSE2-NEXT: retq
;
; SSSE3-LABEL: PR43227:
; SSSE3: # %bb.0:
; SSSE3-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast. getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements. I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.
2020-07-29 12:32:07 +02:00
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
; SSSE3-NEXT: xorps %xmm1, %xmm1
; SSSE3-NEXT: xorps %xmm2, %xmm2
; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]
; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSSE3-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm0[0]
; SSSE3-NEXT: movaps %xmm1, 672(%rsi)
; SSSE3-NEXT: movaps %xmm2, 688(%rsi)
; SSSE3-NEXT: retq
;
; SSE41-LABEL: PR43227:
; SSE41: # %bb.0:
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227) As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset. Until we can properly handle this, we must bail from EltsFromConsecutiveLoads. llvm-svn: 371078
2019-09-05 17:07:07 +02:00
; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast. getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements. I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.
2020-07-29 12:32:07 +02:00
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227) As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset. Until we can properly handle this, we must bail from EltsFromConsecutiveLoads. llvm-svn: 371078
2019-09-05 17:07:07 +02:00
; SSE41-NEXT: pxor %xmm1, %xmm1
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]
; SSE41-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
; SSE41-NEXT: movdqa %xmm1, 672(%rsi)
; SSE41-NEXT: movdqa %xmm0, 688(%rsi)
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
; SSE41-NEXT: retq
;
; AVX-LABEL: PR43227:
; AVX: # %bb.0:
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227) As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset. Until we can properly handle this, we must bail from EltsFromConsecutiveLoads. llvm-svn: 371078
2019-09-05 17:07:07 +02:00
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks If the mask input to getV4X86ShuffleImm8 only refers to a single source element (+ undefs) then canonicalize to a full broadcast. getV4X86ShuffleImm8 defaults to inline values for undefs, which can be useful for shuffle widening/narrowing but does leave SimplifyDemanded* calls thinking the shuffle depends on unnecessary elements. I'm still investigating what we should do more generally to avoid these undemanded elements, but broadcast cases was a simpler win.
2020-07-29 12:32:07 +02:00
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,1,1,1]
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227) As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset. Until we can properly handle this, we must bail from EltsFromConsecutiveLoads. llvm-svn: 371078
2019-09-05 17:07:07 +02:00
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
[X86][SSE] EltsFromConsecutiveLoads - ignore non-zero offset base loads (PR43227) As discussed on D64551 and PR43227, we don't correctly handle cases where the base load has a non-zero byte offset. Until we can properly handle this, we must bail from EltsFromConsecutiveLoads. llvm-svn: 371078
2019-09-05 17:07:07 +02:00
; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
[X86][SSE] Add (failing) test case for PR43227 llvm-svn: 371061
2019-09-05 14:36:11 +02:00
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; AVX-NEXT: vmovaps %ymm0, 672(%rsi)
; AVX-NEXT: vzeroupper
; AVX-NEXT: retq
%1 = getelementptr i32, i32* %explicit_0, i64 63
%2 = bitcast i32* %1 to <3 x i32>*
%3 = load <3 x i32>, <3 x i32>* %2, align 1
%4 = shufflevector <3 x i32> %3, <3 x i32> undef, <2 x i32> <i32 1, i32 2>
%5 = shufflevector <2 x i32> %4, <2 x i32> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%6 = shufflevector <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 undef, i32 0>, <8 x i32> %5, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 5, i32 9, i32 7>
%7 = getelementptr inbounds <8 x i32>, <8 x i32>* %explicit_1, i64 21
store <8 x i32> %6, <8 x i32>* %7, align 32
ret void
}
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