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llvm-mirror/test/CodeGen/X86/mmx-vzmovl-2.ll

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Mark all these as needing SSE2. Should fix PPC and maybe even Linux. llvm-svn: 115291
2010-10-01 06:17:55 +02:00
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep pxor
; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep punpckldq
Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. llvm-svn: 60499
2008-12-03 20:38:05 +01:00
%struct.vS1024 = type { [8 x <4 x i32>] }
%struct.vS512 = type { [4 x <4 x i32>] }
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
declare x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx, i32) nounwind readnone
Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. llvm-svn: 60499
2008-12-03 20:38:05 +01:00
define void @t() nounwind {
entry:
br label %bb554
bb554: ; preds = %bb554, %entry
%sum.0.reg2mem.0 = phi <1 x i64> [ %tmp562, %bb554 ], [ zeroinitializer, %entry ] ; <<1 x i64>> [#uses=1]
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
%0 = load x86_mmx* null, align 8 ; <<1 x i64>> [#uses=2]
%1 = bitcast x86_mmx %0 to <2 x i32> ; <<2 x i32>> [#uses=1]
Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. llvm-svn: 60499
2008-12-03 20:38:05 +01:00
%tmp555 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1]
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
%2 = bitcast <2 x i32> %tmp555 to x86_mmx ; <<1 x i64>> [#uses=1]
%3 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %0, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
Previously, RecursivelyDeleteDeadInstructions provided an option of returning a list of pointers to Values that are deleted. This was unsafe, because the pointers in the list are, by nature of what RecursivelyDeleteDeadInstructions does, always dangling. Replace this with a simple callback mechanism. This may eventually be removed if all clients can reasonably be expected to use CallbackVH. Use this to factor out the dead-phi-cycle-elimination code from LSR utility function, and generalize it to use the RecursivelyDeleteTriviallyDeadInstructions utility function. This makes LSR more aggressive about eliminating dead PHI cycles; adjust tests to either be less trivial or to simply expect fewer instructions. llvm-svn: 70636
2009-05-02 20:29:22 +02:00
store <1 x i64> %sum.0.reg2mem.0, <1 x i64>* null
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
%tmp3 = bitcast x86_mmx %2 to <1 x i64>
%tmp558 = add <1 x i64> %sum.0.reg2mem.0, %tmp3 ; <<1 x i64>> [#uses=1]
%tmp5 = bitcast <1 x i64> %tmp558 to x86_mmx
%4 = call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %tmp5, i32 32) nounwind readnone ; <<1 x i64>> [#uses=1]
%tmp6 = bitcast x86_mmx %4 to <1 x i64>
%tmp7 = bitcast x86_mmx %3 to <1 x i64>
%tmp562 = add <1 x i64> %tmp6, %tmp7 ; <<1 x i64>> [#uses=1]
Use mmx (punpckldq VR64, (mmx_v_set0)) to clear high 32-bits of a VR64 register. llvm-svn: 60499
2008-12-03 20:38:05 +01:00
br label %bb554
}
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