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llvm-mirror/test/CodeGen/PowerPC/testCompareslleqsll.ll

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[PowerPC] Eliminate integer compare instructions - vol. 3 This patch builds upon https://reviews.llvm.org/rL302810 to add handling for the 64-bit SETEQ patterns. Differential Revision: https://reviews.llvm.org/D33369 llvm-svn: 304286
2017-05-31 10:04:07 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 14:39:10 +01:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Eliminate integer compare instructions - vol. 3 This patch builds upon https://reviews.llvm.org/rL302810 to add handling for the 64-bit SETEQ patterns. Differential Revision: https://reviews.llvm.org/D33369 llvm-svn: 304286
2017-05-31 10:04:07 +02:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
[PowerPC] Recommit r314244 with refactoring and off by default This re-commits everything that was pulled in r314244. The transformation is off by default (patch to enable it to follow). The code is refactored to have a single entry-point and provide fine-grained control over patterns that it selects. This patch also fixes the bugs in the original code. Everything that failed with the original patch has been re-tested with this patch (with the transformation turned on). So the patch to turn this on is soon to follow. Differential Revision: https://reviews.llvm.org/D38575 llvm-svn: 319434
2017-11-30 14:39:10 +01:00
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
[PowerPC] Eliminate integer compare instructions - vol. 3 This patch builds upon https://reviews.llvm.org/rL302810 to add handling for the 64-bit SETEQ patterns. Differential Revision: https://reviews.llvm.org/D33369 llvm-svn: 304286
2017-05-31 10:04:07 +02:00
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = common local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind readnone
define i64 @test_lleqsll_sext_z(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
ret i64 %conv1
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_lleqsll_sext_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: xor r3, r3, r4
; CHECK-NEXT: ld r12, .LC0@toc@l(r5)
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r12)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, %b
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: cntlzd r3, r3
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: rldicl r3, r3, 58, 63
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
; Function Attrs: norecurse nounwind
define void @test_lleqsll_sext_z_store(i64 %a) {
; CHECK-LABEL: test_lleqsll_sext_z_store:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
; CHECK-NEXT: addic r3, r3, -1
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr
entry:
%cmp = icmp eq i64 %a, 0
%conv1 = sext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8
ret void
}
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