llvm-mirror/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# XFAIL: *

# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
# -------------------------------------------------------------------------------------------------
# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# A8.6.167
# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE
0x1b 0x68 0xf 0x97
Should also check SMLAD for invalid register values. rdar://problem/9246650 llvm-svn: 129042 2011-04-07 02:50:25 +02:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 \|& grep {invalid instruction encoding}`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144 2011-08-09 22:55:18 +02:00			`# XFAIL: *`
Should also check SMLAD for invalid register values. rdar://problem/9246650 llvm-svn: 129042 2011-04-07 02:50:25 +02:00
			`# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1)`
			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 0: 0: 1\| 0: 1: 1: 1\| 0: 0: 0: 0\| 1: 1: 1: 1\| 0: 1: 1: 0\| 1: 0: 0: 0\| 0: 0: 0: 1\| 1: 0: 1: 1\|`
			`# -------------------------------------------------------------------------------------------------`
			`#`
			`# A8.6.167`
			`# if d == 15 \|\| n == 15 \| m == 15 then UNPREDICTABLE`
			`0x1b 0x68 0xf 0x97`