llvm-mirror/test/CodeGen/MIR/X86/expected-machine-operand.mir

# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s

--- |

  define i32 @foo() {
  entry:
    ret i32 0
  }

...
---
name:            foo
body:
 - id:           0
   name:         entry
   instructions:
     # CHECK: [[@LINE+1]]:24: expected a machine operand
     - '%eax = XOR32rr ='
     - 'RETQ %eax'
...
MIR Serialization: Serialize physical register machine operands. This commit introduces functionality that's used to serialize machine operands. Only the physical register operands are serialized by this commit. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10525 llvm-svn: 240425 2015-06-23 18:35:26 +02:00			`# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 \| FileCheck %s`

			`--- \|`

			`define i32 @foo() {`
			`entry:`
			`ret i32 0`
			`}`

			`...`
			`---`
			`name: foo`
			`body:`
MIR Serialization: Serialize machine basic block operands. This commit serializes machine basic block operands. The machine basic block operands use the following syntax: %bb.<id>[.<name>] This commit also modifies the YAML representation for the machine basic blocks - a new, required field 'id' is added to the MBB YAML mapping. The id is used to resolve the MBB references to the actual MBBs. And while the name of the MBB can be included in a MBB reference, this name isn't used to resolve MBB references - as it's possible that multiple MBBs will reference the same BB and thus they will have the same name. If the name is specified, the parser will verify that it is equal to the name of the MBB with the specified id. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10608 llvm-svn: 240792 2015-06-26 18:46:11 +02:00			`- id: 0`
			`name: entry`
MIR Serialization: Serialize physical register machine operands. This commit introduces functionality that's used to serialize machine operands. Only the physical register operands are serialized by this commit. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10525 llvm-svn: 240425 2015-06-23 18:35:26 +02:00			`instructions:`
MIR Parser: Use correct source locations for machine instruction diagnostics. This commit translates the source locations for MIParser diagnostics from the locations in the machine instruction string to the locations in the MIR file. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10574 llvm-svn: 240474 2015-06-24 00:39:23 +02:00			`# CHECK: [[@LINE+1]]:24: expected a machine operand`
MIR Serialization: Serialize physical register machine operands. This commit introduces functionality that's used to serialize machine operands. Only the physical register operands are serialized by this commit. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10525 llvm-svn: 240425 2015-06-23 18:35:26 +02:00			`- '%eax = XOR32rr ='`
			`- 'RETQ %eax'`
			`...`