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llvm-mirror/test/CodeGen/PowerPC/fast-isel-pcrel.ll

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[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O0 -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -fast-isel -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
%struct._IO_FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct._IO_FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
%struct._IO_marker = type { %struct._IO_marker*, %struct._IO_FILE*, i32 }
@.str = private unnamed_addr constant [25 x i8] c"Breaking the TOC for FP\0A\00", align 1
@.str.1 = private unnamed_addr constant [25 x i8] c"Breaking the TOC for GV\0A\00", align 1
@stdout = external global %struct._IO_FILE*, align 8
; Function Attrs: noinline nounwind optnone
define internal void @loadFP(double* %d) #0 {
; CHECK-LABEL: loadFP:
[PowerPC] Do not use FISel for calls and TOC-based accesses with PC-Rel PC-Relative addressing introduces a fair bit of complexity for correctly eliminating TOC accesses. FastISel does not include any of that handling so we miscompile code with -mcpu=pwr10 -O0 if it includes an external call that FastISel does not handle followed by any of the following: Floating point constant materialization Materialization of a GlobalValue Call that FastISel does handle This patch switches to SDISel for any of the above. Differential revision: https://reviews.llvm.org/D86343
2020-08-24 23:51:19 +02:00
; CHECK: .localentry loadFP, 1
; CHECK-NEXT: # %bb.0: # %entry
[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -112(r1)
; CHECK-NEXT: std r3, 104(r1)
; CHECK-NEXT: paddi r3, 0, .L.str@PCREL, 1
; CHECK-NEXT: bl printf@notoc
; CHECK-NEXT: ld r4, 104(r1)
[PowerPC] Exploit paddi instruction on Power 10 for constant materialization Starting with Power 10 the instruction paddi is available to use. The instruction allows for immediates that are 34 bits. This patch adds exploitation of the paddi instruction to allow us to materialize constants. Reviewed By: lei, amyk Differential Revision: https://reviews.llvm.org/D93300
2021-03-11 12:44:55 +01:00
; CHECK-NEXT: pli r5, 1075049922
; CHECK-NEXT: pli r3, 2405181686
; CHECK-NEXT: rldimi r3, r5, 32, 0
Reapply "RegAllocFast: Rewrite and improve" This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
2020-09-22 14:55:54 +02:00
; CHECK-NEXT: std r3, 0(r4)
[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; CHECK-NEXT: addi r1, r1, 112
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
%d.addr = alloca double*, align 8
store double* %d, double** %d.addr, align 8
%call = call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str, i64 0, i64 0))
%0 = load double*, double** %d.addr, align 8
store double 4.990000e+00, double* %0, align 8
ret void
}
declare signext i32 @printf(i8*, ...)
; Function Attrs: noinline nounwind optnone
define internal void @loadGV() #0 {
; CHECK-LABEL: loadGV:
[PowerPC] Do not use FISel for calls and TOC-based accesses with PC-Rel PC-Relative addressing introduces a fair bit of complexity for correctly eliminating TOC accesses. FastISel does not include any of that handling so we miscompile code with -mcpu=pwr10 -O0 if it includes an external call that FastISel does not handle followed by any of the following: Floating point constant materialization Materialization of a GlobalValue Call that FastISel does handle This patch switches to SDISel for any of the above. Differential revision: https://reviews.llvm.org/D86343
2020-08-24 23:51:19 +02:00
; CHECK: .localentry loadGV, 1
; CHECK-NEXT: # %bb.0: # %entry
[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
Reapply "RegAllocFast: Rewrite and improve" This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
2020-09-22 14:55:54 +02:00
; CHECK-NEXT: stdu r1, -96(r1)
[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; CHECK-NEXT: paddi r3, 0, .L.str.1@PCREL, 1
; CHECK-NEXT: bl printf@notoc
Reapply "RegAllocFast: Rewrite and improve" This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
2020-09-22 14:55:54 +02:00
; CHECK-NEXT: pld r3, stdout@got@pcrel(0), 1
; CHECK-NEXT: ld r4, 0(r3)
; CHECK-NEXT: li r3, 97
[PowerPC] Do not use FISel for calls and TOC-based accesses with PC-Rel PC-Relative addressing introduces a fair bit of complexity for correctly eliminating TOC accesses. FastISel does not include any of that handling so we miscompile code with -mcpu=pwr10 -O0 if it includes an external call that FastISel does not handle followed by any of the following: Floating point constant materialization Materialization of a GlobalValue Call that FastISel does handle This patch switches to SDISel for any of the above. Differential revision: https://reviews.llvm.org/D86343
2020-08-24 23:51:19 +02:00
; CHECK-NEXT: bl _IO_putc@notoc
Reapply "RegAllocFast: Rewrite and improve" This reverts commit 73a6a164b84a8195defbb8f5eeb6faecfc478ad4.
2020-09-22 14:55:54 +02:00
; CHECK-NEXT: addi r1, r1, 96
[PowerPC] Pre-commit FISel with PC-Rel test Our handling of PC-Relative addressing is currently broken with Fast ISel in 3 ways: - FISel emits calls without handling all the PC-Rel intricacies - FISel materializes FP constants through the TOC - FISel materializes GV's through the TOC As it would be unnecessarily tedious to implement all the handling for PC-Rel in Fast ISel, we will turn off FISel for anything that generates references to the TOC.
2020-08-21 13:13:56 +02:00
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
%call = call signext i32 (i8*, ...) @printf(i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str.1, i64 0, i64 0))
%0 = load %struct._IO_FILE*, %struct._IO_FILE** @stdout, align 8
%call1 = call signext i32 @_IO_putc(i32 signext 97, %struct._IO_FILE* %0)
ret void
}
declare signext i32 @_IO_putc(i32 signext, %struct._IO_FILE*)
attributes #0 = { noinline nounwind optnone }
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