llvm-mirror/test/CodeGen/X86/inline-asm-2addr.ll

; RUN: llc < %s -march=x86-64 | not grep movq

define i64 @t(i64 %a, i64 %b) nounwind ssp {
entry:
	%asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind		; <i64> [#uses=1]
	%asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind		; <i64> [#uses=1]
	%0 = add i64 %asmtmp1, %asmtmp		; <i64> [#uses=1]
	ret i64 %0
}
Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81290 2009-09-09 01:54:48 +02:00			`; RUN: llc < %s -march=x86-64 \| not grep movq`
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. llvm-svn: 67512 2009-03-23 09:01:15 +01:00
			`define i64 @t(i64 %a, i64 %b) nounwind ssp {`
			`entry:`
			`%asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind ; <i64> [#uses=1]`
			`%asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind ; <i64> [#uses=1]`
			`%0 = add i64 %asmtmp1, %asmtmp ; <i64> [#uses=1]`
			`ret i64 %0`
			`}`