llvm-mirror/test/CodeGen/ARM/2009-05-18-InlineAsmMem.ll

; RUN: llc < %s -march=arm | FileCheck %s
; RUN: llc < %s -march=thumb | FileCheck %s
; PR4091

define void @foo(i32 %i, i32* %p) nounwind {
;CHECK: swp r2, r0, [r1]
	%asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=*m,r,*m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind
	ret void
}
Revise ARM inline assembly memory operands to require the memory address to be in a register. The previous use of ARM address mode 2 was completely arbitrary and inappropriate for Thumb. Radar 7137468. llvm-svn: 84022 2009-10-13 22:50:28 +02:00			`; RUN: llc < %s -march=arm \| FileCheck %s`
			`; RUN: llc < %s -march=thumb \| FileCheck %s`
Fix pr4091: Add support for "m" constraint in ARM inline assembly. llvm-svn: 72105 2009-05-19 07:53:42 +02:00			`; PR4091`

			`define void @foo(i32 %i, i32* %p) nounwind {`
Revise ARM inline assembly memory operands to require the memory address to be in a register. The previous use of ARM address mode 2 was completely arbitrary and inappropriate for Thumb. Radar 7137468. llvm-svn: 84022 2009-10-13 22:50:28 +02:00			`;CHECK: swp r2, r0, [r1]`
Fix pr4091: Add support for "m" constraint in ARM inline assembly. llvm-svn: 72105 2009-05-19 07:53:42 +02:00			`%asmtmp = call i32 asm sideeffect "swp $0, $2, $3", "=&r,=m,r,m,~{memory}"(i32* %p, i32 %i, i32* %p) nounwind`
			`ret void`
			`}`