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llvm-mirror/test/CodeGen/X86/add.ll

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Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
2012-02-02 00:20:51 +01:00
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s -check-prefix=X32
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 01:44:19 +02:00
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64
consolidate and filecheckize two tests. llvm-svn: 95652
2010-02-09 07:24:00 +01:00
; The immediate can be encoded in a smaller way if the
; instruction is a sub instead of an add.
define i32 @test1(i32 inreg %a) nounwind {
%b = add i32 %a, 128
ret i32 %b
; X32: subl $-128, %eax
; X64: subl $-128,
}
define i64 @test2(i64 inreg %a) nounwind {
%b = add i64 %a, 2147483648
ret i64 %b
; X32: addl $-2147483648, %eax
; X64: subq $-2147483648,
}
define i64 @test3(i64 inreg %a) nounwind {
%b = add i64 %a, 128
ret i64 %b
; X32: addl $128, %eax
; X64: subq $-128,
}
merge another test in, drop the trivially constant folded cases. llvm-svn: 95653
2010-02-09 07:33:27 +01:00
define i1 @test4(i32 %v1, i32 %v2, i32* %X) nounwind {
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%sum = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
br i1 %obit, label %overflow, label %normal
normal:
store i32 0, i32* %X
br label %overflow
overflow:
ret i1 false
; X32: test4:
; X32: addl
; X32-NEXT: jo
; X64: test4:
Relax expressions and add explicit triplets -linux and -win32. llvm-svn: 126196
2011-02-22 08:19:12 +01:00
; X64: addl %e[[A1:si|dx]], %e[[A0:di|cx]]
merge another test in, drop the trivially constant folded cases. llvm-svn: 95653
2010-02-09 07:33:27 +01:00
; X64-NEXT: jo
}
define i1 @test5(i32 %v1, i32 %v2, i32* %X) nounwind {
entry:
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%sum = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
br i1 %obit, label %carry, label %normal
normal:
store i32 0, i32* %X
br label %carry
carry:
ret i1 false
; X32: test5:
; X32: addl
; X32-NEXT: jb
; X64: test5:
Relax expressions and add explicit triplets -linux and -win32. llvm-svn: 126196
2011-02-22 08:19:12 +01:00
; X64: addl %e[[A1]], %e[[A0]]
merge another test in, drop the trivially constant folded cases. llvm-svn: 95653
2010-02-09 07:33:27 +01:00
; X64-NEXT: jb
}
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32)
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32)
merge a target-specific add test into x86 directory. llvm-svn: 95654
2010-02-09 07:35:50 +01:00
define i64 @test6(i64 %A, i32 %B) nounwind {
%tmp12 = zext i32 %B to i64 ; <i64> [#uses=1]
%tmp3 = shl i64 %tmp12, 32 ; <i64> [#uses=1]
%tmp5 = add i64 %tmp3, %A ; <i64> [#uses=1]
ret i64 %tmp5
; X32: test6:
; X32: movl 12(%esp), %edx
; X32-NEXT: addl 8(%esp), %edx
; X32-NEXT: movl 4(%esp), %eax
; X32-NEXT: ret
; X64: test6:
Relax expressions and add explicit triplets -linux and -win32. llvm-svn: 126196
2011-02-22 08:19:12 +01:00
; X64: shlq $32, %r[[A1]]
; X64: leaq (%r[[A1]],%r[[A0]]), %rax
merge a target-specific add test into x86 directory. llvm-svn: 95654
2010-02-09 07:35:50 +01:00
; X64: ret
}
We lower setb to sbb with the hope that the and will go away, when it doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret llvm-svn: 122217
2010-12-20 02:16:03 +01:00
define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind {
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
ret {i32, i1} %t
}
; X64: test7:
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 01:44:19 +02:00
; X64: addl %e[[A1]], %e
We lower setb to sbb with the hope that the and will go away, when it doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret llvm-svn: 122217
2010-12-20 02:16:03 +01:00
; X64-NEXT: setb %dl
Remove -join-physregs from the test suite. This option has been disabled for a while, and it is going away so I can clean up the coalescer code. The tests that required physreg joining to be enabled were almost all of the form "tiny function with interference between arguments and return value". Such functions are usually inlined in the real world. The problem exposed by phys_subreg_coalesce-3.ll is real, but fairly rare. llvm-svn: 157027
2012-05-18 01:44:19 +02:00
; X64: ret
now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results, the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is a step towards finishing off PR5443. In the testcase in that bug we now get: movq %rdi, %rax addq %rsi, %rax sbbq %rcx, %rcx testb $1, %cl setne %dl ret instead of: movq %rdi, %rax addq %rsi, %rax movl $0, %ecx adcq $0, %rcx testq %rcx, %rcx setne %dl ret llvm-svn: 122219
2010-12-20 02:37:09 +01:00
; PR5443
define {i64, i1} @test8(i64 %left, i64 %right) nounwind {
entry:
%extleft = zext i64 %left to i65
%extright = zext i64 %right to i65
%sum = add i65 %extleft, %extright
%res.0 = trunc i65 %sum to i64
%overflow = and i65 %sum, -18446744073709551616
%res.1 = icmp ne i65 %overflow, 0
%final0 = insertvalue {i64, i1} undef, i64 %res.0, 0
%final1 = insertvalue {i64, i1} %final0, i1 %res.1, 1
ret {i64, i1} %final1
}
; X64: test8:
; X64: addq
; X64-NEXT: sbbq
; X64-NEXT: testb
DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] llvm-svn: 122455
2010-12-23 00:17:45 +01:00
define i32 @test9(i32 %x, i32 %y) nounwind readnone {
%cmp = icmp eq i32 %x, 10
%sub = sext i1 %cmp to i32
%cond = add i32 %sub, %y
ret i32 %cond
; X64: test9:
; X64: cmpl $10
; X64: sete
; X64: subl
; X64: ret
}
X86: Fix the (saddo/ssub x, 1) -> incl/decl selection to check the right operand for 1. Found by inspection. llvm-svn: 127247
2011-03-08 16:20:20 +01:00
define i1 @test10(i32 %x) nounwind {
entry:
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %x, i32 1)
%obit = extractvalue {i32, i1} %t, 1
ret i1 %obit
; X32: test10:
; X32: incl
; X32-NEXT: seto
; X64: test10:
; X64: incl
; X64-NEXT: seto
}
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