llvm-mirror/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt

# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}

# Opcode=0 Name=PHI Format=(42)
#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
#
# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
0x92 0xb4 0x1f 0xdc
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which amounts to an UNDEFINED instruction. llvm-svn: 128668 2011-03-31 22:54:30 +02:00			`# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 \|& grep {invalid instruction encoding}`

			`# Opcode=0 Name=PHI Format=(42)`
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144 2011-08-09 22:55:18 +02:00			`# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0`
Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, which amounts to an UNDEFINED instruction. llvm-svn: 128668 2011-03-31 22:54:30 +02:00			`# -------------------------------------------------------------------------------------------------`
			`# \| 1: 1: 0: 1\| 1: 1: 0: 0\| 0: 0: 0: 1\| 1: 1: 1: 1\| 1: 0: 1: 1\| 0: 1: 0: 0\| 1: 0: 0: 1\| 0: 0: 1: 0\|`
			`# -------------------------------------------------------------------------------------------------`
			`#`
			`# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.`
			`0x92 0xb4 0x1f 0xdc`