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llvm-mirror/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll

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[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
declare void @callee(i8*, i32*)
define void @caller(i32 %n) {
; RV32I-LABEL: caller:
; RV32I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV32I-NEXT: addi sp, sp, -64
; RV32I-NEXT: .cfi_def_cfa_offset 64
; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: .cfi_offset s0, -8
; RV32I-NEXT: .cfi_offset s1, -12
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV32I-NEXT: addi s0, sp, 64
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV32I-NEXT: .cfi_def_cfa s0, 0
; RV32I-NEXT: andi sp, sp, -64
; RV32I-NEXT: mv s1, sp
; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0
; RV32I-NEXT: mv sp, a0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV32I-NEXT: mv a1, s1
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV32I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV32I-NEXT: addi sp, s0, -64
; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV32I-NEXT: ret
;
; RV64I-LABEL: caller:
; RV64I: # %bb.0:
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: .cfi_def_cfa_offset 64
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: .cfi_offset s0, -16
; RV64I-NEXT: .cfi_offset s1, -24
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV64I-NEXT: addi s0, sp, 64
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV64I-NEXT: .cfi_def_cfa s0, 0
; RV64I-NEXT: andi sp, sp, -64
; RV64I-NEXT: mv s1, sp
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: addi a0, a0, 15
[RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND immediates. SimplifyDemandedBits can remove set bits from immediates from instructions like AND/OR/XOR. This can prevent them from being efficiently codegened on RISCV. This adds an initial version that tries to keep or form 12 bit sign extended immediates for AND operations to enable use of ANDI. If that doesn't work we'll try to create a 32 bit sign extended immediate to use LUI+ADDIW. More optimizations are possible for different size immediates or different operations. But this is a good starting point that already has test coverage. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D94628
2021-01-15 19:54:26 +01:00
; RV64I-NEXT: andi a0, a0, -16
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV64I-NEXT: sub a0, sp, a0
; RV64I-NEXT: mv sp, a0
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV64I-NEXT: mv a1, s1
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-09 20:41:19 +01:00
; RV64I-NEXT: call callee@plt
[RISCV] Do not grow the stack a second time when we need to realign the stack This is a first change needed to fix a crash in which the emergency spill splot ends being out of reach. This happens when we run the register scavenger after we have eliminated the frame indexes. The fix for the actual crash will come in a later change. This change removes an extra stack size increase we do in RISCVFrameLowering::determineFrameLayout. We don't have to change the size of the stack here as PEI::calculateFrameObjectOffsets is already doing this with the right size accounting the extra alignment. Differential Revision: https://reviews.llvm.org/D89237
2021-01-09 17:49:05 +01:00
; RV64I-NEXT: addi sp, s0, -64
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64
[RISCV] Handle variable sized objects with the stack need to be realigned Differential Revision: https://reviews.llvm.org/D68979
2019-10-15 09:11:35 +02:00
; RV64I-NEXT: ret
%1 = alloca i8, i32 %n
%2 = alloca i32, align 64
call void @callee(i8* %1, i32 *%2)
ret void
}
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