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llvm-mirror/test/CodeGen/X86/x86-64-and-mask.ll

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Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it has an immediate with at least 32 bits of leading zeros, to avoid needing to materialize that immediate in a register first. FileCheckize, tidy, and extend a testcase to cover this case. This fixes rdar://7527390. llvm-svn: 93160
2010-01-11 18:58:34 +01:00
; RUN: llc < %s | FileCheck %s
Compile x86-64-and-mask.ll into: _test: movl %edi, %eax ret instead of: _test: movl $4294967295, %ecx movq %rdi, %rax andq %rcx, %rax ret It would be great to write this as a Pat pattern that used subregs instead of a 'pseudo' instruction, but I don't know how to do that in td files. llvm-svn: 47658
2008-02-27 06:47:54 +01:00
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin8"
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it has an immediate with at least 32 bits of leading zeros, to avoid needing to materialize that immediate in a register first. FileCheckize, tidy, and extend a testcase to cover this case. This fixes rdar://7527390. llvm-svn: 93160
2010-01-11 18:58:34 +01:00
; This should be a single mov, not a load of immediate + andq.
; CHECK: test:
; CHECK: movl %edi, %eax
define i64 @test(i64 %x) nounwind {
Compile x86-64-and-mask.ll into: _test: movl %edi, %eax ret instead of: _test: movl $4294967295, %ecx movq %rdi, %rax andq %rcx, %rax ret It would be great to write this as a Pat pattern that used subregs instead of a 'pseudo' instruction, but I don't know how to do that in td files. llvm-svn: 47658
2008-02-27 06:47:54 +01:00
entry:
%tmp123 = and i64 %x, 4294967295 ; <i64> [#uses=1]
ret i64 %tmp123
}
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it has an immediate with at least 32 bits of leading zeros, to avoid needing to materialize that immediate in a register first. FileCheckize, tidy, and extend a testcase to cover this case. This fixes rdar://7527390. llvm-svn: 93160
2010-01-11 18:58:34 +01:00
; This copy can't be coalesced away because it needs the implicit zero-extend.
; CHECK: bbb:
; CHECK: movl %edi, %edi
define void @bbb(i64 %x) nounwind {
%t = and i64 %x, 4294967295
call void @foo(i64 %t)
ret void
}
; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
; with a separate mov to materialize the mask.
; rdar://7527390
; CHECK: ccc:
; CHECK: andl $-1048593, %edi
declare void @foo(i64 %x) nounwind
define void @ccc(i64 %x) nounwind {
%t = and i64 %x, 4293918703
call void @foo(i64 %t)
ret void
}
; This requires a mov and a 64-bit and.
; CHECK: ddd:
Fix a batch of x86 tests to be coalescer independent. Most of these tests require a single mov instruction that can come either before or after a 2-addr instruction. -join-physregs changes the behavior, but the results are equivalent. llvm-svn: 130891
2011-05-05 01:54:51 +02:00
; CHECK: movabsq $4294967296, %r
Use a 32-bit and with implicit zero-extension instead of a 64-bit and if it has an immediate with at least 32 bits of leading zeros, to avoid needing to materialize that immediate in a register first. FileCheckize, tidy, and extend a testcase to cover this case. This fixes rdar://7527390. llvm-svn: 93160
2010-01-11 18:58:34 +01:00
; CHECK: andq %rax, %rdi
define void @ddd(i64 %x) nounwind {
%t = and i64 %x, 4294967296
call void @foo(i64 %t)
ret void
}
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