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llvm-mirror/test/MC/VE/LFRSFR.s

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[VE] Support control instructions in MC layer Summary: Add regression tests of asmparser, mccodeemitter, and disassembler for control instructions. Add not defined LPM/SPM/LFR/SFR/SMIR/NOP/LCR/ SCR/TSCR/FIDCR control isntructions newly. Define MISC registers which SMIR instruction reads and IC register which SIC instruction reads. Change asmparser to support Zero, UImm3, and UImm6 operands and MISC registers. Change instprinter to support MISC registers also. Change to use auto to receive dyn_cast also. Differential Revision: https://reviews.llvm.org/D81370
2020-06-08 11:41:41 +02:00
# RUN: llvm-mc -triple=ve --show-encoding < %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
# RUN: | FileCheck %s --check-prefixes=CHECK-INST
# CHECK-INST: lfr %s11
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x8b,0x00,0x69]
lfr %s11
# CHECK-INST: lfr 63
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x3f,0x00,0x69]
lfr 63
# CHECK-INST: sfr %s63
# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0x29]
sfr %s63
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