2016-02-19 01:18:46 +01:00
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# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
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2015-08-11 02:32:49 +02:00
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# This test ensures that the MIR parser parses the callee saved register mask
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# correctly and that the MIR parser can infer it as well.
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--- |
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define i32 @compute(i32 %a) #0 {
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body:
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%c = mul i32 %a, 11
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ret i32 %c
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}
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define i32 @foo(i32 %a) #0 {
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entry:
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%b = call i32 @compute(i32 %a)
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ret i32 %b
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}
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define i32 @bar(i32 %a) #0 {
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entry:
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%b = call i32 @compute(i32 %a)
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ret i32 %b
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}
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define i32 @empty(i32 %a) #0 {
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entry:
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%b = call i32 @compute(i32 %a)
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ret i32 %b
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}
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attributes #0 = { "no-frame-pointer-elim"="false" }
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...
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---
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# CHECK: name: compute
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# CHECK: liveins:
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# CHECK-NEXT: - { reg: '%edi' }
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# CHECK-NEXT: frameInfo:
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name: compute
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liveins:
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- { reg: '%edi' }
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frameInfo:
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stackSize: 8
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2015-08-14 01:10:16 +02:00
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body: |
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bb.0.body:
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liveins: %edi
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%eax = IMUL32rri8 %edi, 11, implicit-def %eflags
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RETQ %eax
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2015-08-11 02:32:49 +02:00
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...
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---
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name: foo
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liveins:
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- { reg: '%edi' }
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# CHECK: name: foo
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# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
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# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
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# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
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# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
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calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
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'%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
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'%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
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'%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
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2015-08-14 01:10:16 +02:00
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body: |
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bb.0.entry:
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liveins: %edi
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PUSH64r %rax, implicit-def %rsp, implicit %rsp
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CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
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%rdx = POP64r implicit-def %rsp, implicit %rsp
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RETQ %eax
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2015-08-11 02:32:49 +02:00
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...
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---
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name: bar
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liveins:
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- { reg: '%edi' }
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# Verify that the callee saved register can be inferred from register mask
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# machine operands:
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# CHECK: name: bar
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# CHECK: calleeSavedRegisters: [ '%bh', '%bl', '%bp', '%bpl', '%bx', '%ebp', '%ebx',
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# CHECK-NEXT: '%rbp', '%rbx', '%r12', '%r13', '%r14', '%r15',
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# CHECK-NEXT: '%r12b', '%r13b', '%r14b', '%r15b', '%r12d', '%r13d',
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# CHECK-NEXT: '%r14d', '%r15d', '%r12w', '%r13w', '%r14w', '%r15w' ]
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2015-08-14 01:10:16 +02:00
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body: |
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bb.0.entry:
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liveins: %edi
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PUSH64r %rax, implicit-def %rsp, implicit %rsp
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CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
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%rdx = POP64r implicit-def %rsp, implicit %rsp
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RETQ %eax
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2015-08-11 02:32:49 +02:00
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...
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---
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name: empty
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liveins:
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- { reg: '%edi' }
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# Verify that the callee saved register can be empty.
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# CHECK: name: empty
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# CHECK: calleeSavedRegisters: [ ]
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calleeSavedRegisters: [ ]
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2015-08-14 01:10:16 +02:00
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body: |
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bb.0.entry:
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liveins: %edi
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PUSH64r %rax, implicit-def %rsp, implicit %rsp
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CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
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%rdx = POP64r implicit-def %rsp, implicit %rsp
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RETQ %eax
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2015-08-11 02:32:49 +02:00
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...
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