mirror of
https://github.com/RPCS3/llvm-mirror.git
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286 lines
8.0 KiB
LLVM
286 lines
8.0 KiB
LLVM
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; RUN: opt -S -gvn-hoist < %s | FileCheck %s
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; Checking gvn-hoist in case of indirect branches.
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; Check that the bitcast is not hoisted because it is after an indirect call
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; CHECK-LABEL: @foo
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; CHECK-LABEL: l1.preheader:
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; CHECK-NEXT: bitcast
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; CHECK-LABEL: l1
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; CHECK: bitcast
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%class.bar = type { i8*, %class.base* }
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%class.base = type { i32 (...)** }
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@bar = local_unnamed_addr global i32 ()* null, align 8
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@bar1 = local_unnamed_addr global i32 ()* null, align 8
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define i32 @foo(i32* nocapture readonly %i) {
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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%0 = load i32, i32* %i, align 4
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%.off = add i32 %0, -1
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%switch = icmp ult i32 %.off, 2
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br i1 %switch, label %l1.preheader, label %sw.default
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l1.preheader: ; preds = %sw.default, %entry
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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br label %l1
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l1: ; preds = %l1.preheader, %l1
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%1 = load i32 ()*, i32 ()** @bar, align 8
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%call = tail call i32 %1()
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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br label %l1
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sw.default: ; preds = %entry
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%2 = load i32 ()*, i32 ()** @bar1, align 8
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%call2 = tail call i32 %2()
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br label %l1.preheader
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}
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; Any instruction inside an infinite loop will not be hoisted because
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; there is no path to exit of the function.
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; CHECK-LABEL: @foo1
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; CHECK-LABEL: l1.preheader:
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; CHECK-NEXT: bitcast
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; CHECK-LABEL: l1:
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; CHECK: bitcast
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define i32 @foo1(i32* nocapture readonly %i) {
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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%0 = load i32, i32* %i, align 4
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%.off = add i32 %0, -1
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%switch = icmp ult i32 %.off, 2
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br i1 %switch, label %l1.preheader, label %sw.default
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l1.preheader: ; preds = %sw.default, %entry
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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%y1 = load %class.base*, %class.base** %x, align 8
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br label %l1
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l1: ; preds = %l1.preheader, %l1
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%1 = load i32 ()*, i32 ()** @bar, align 8
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%y2 = load %class.base*, %class.base** %x, align 8
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%call = tail call i32 %1()
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br label %l1
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sw.default: ; preds = %entry
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%2 = load i32 ()*, i32 ()** @bar1, align 8
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%call2 = tail call i32 %2()
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br label %l1.preheader
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}
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; Check that bitcast is hoisted even when one of them is partially redundant.
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; CHECK-LABEL: @test13
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; CHECK: bitcast
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; CHECK-NOT: bitcast
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define i32 @test13(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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store i32 4, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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ret i32 123
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F:
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ret i32 1422
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}
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; Check that the bitcast is not hoisted because anticipability
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; cannot be guaranteed here as one of the indirect branch targets
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; do not have the bitcast instruction.
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; CHECK-LABEL: @test14
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; CHECK-LABEL: B2:
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; CHECK-NEXT: bitcast
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; CHECK-LABEL: BrBlock:
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; CHECK-NEXT: bitcast
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define i32 @test14(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2, label %T]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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store i32 4, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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%pi = load i32, i32* %i, align 4
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ret i32 %pi
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F:
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%pl = load i32, i32* %P
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ret i32 %pl
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}
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; Check that the bitcast is not hoisted because of a cycle
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; due to indirect branches
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; CHECK-LABEL: @test16
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; CHECK-LABEL: B2:
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; CHECK-NEXT: bitcast
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; CHECK-LABEL: BrBlock:
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; CHECK-NEXT: bitcast
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define i32 @test16(i32* %P, i8* %Ptr, i32* nocapture readonly %i) {
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entry:
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%agg.tmp = alloca %class.bar, align 8
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%x= getelementptr inbounds %class.bar, %class.bar* %agg.tmp, i64 0, i32 1
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%y = load %class.base*, %class.base** %x, align 8
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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B2:
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%b1 = bitcast %class.base* %y to void (%class.base*)***
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%0 = load i32, i32* %i, align 4
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store i32 %0, i32 *%P
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br label %BrBlock
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BrBlock:
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%b2 = bitcast %class.base* %y to void (%class.base*)***
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%L = load i32, i32* %P
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%C = icmp eq i32 %L, 42
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br i1 %C, label %T, label %F
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T:
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indirectbr i32* %P, [label %BrBlock, label %B2]
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F:
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indirectbr i8* %Ptr, [label %BrBlock, label %B2]
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}
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@_ZTIi = external constant i8*
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; Check that an instruction is not hoisted out of landing pad (%lpad4)
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; Also within a landing pad no redundancies are removed by gvn-hoist,
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; however an instruction may be hoisted into a landing pad if
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; landing pad has direct branches (e.g., %lpad to %catch1, %catch)
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; This CFG has a cycle (%lpad -> %catch1 -> %lpad4 -> %lpad)
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; CHECK-LABEL: @foo2
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; Check that nothing gets hoisted out of %lpad
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; CHECK-LABEL: lpad:
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; CHECK: %bc1 = add i32 %0, 10
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; CHECK: %bc7 = add i32 %0, 10
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; Check that the add is hoisted
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; CHECK-LABEL: catch1:
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; CHECK-NEXT: invoke
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; Check that the add is hoisted
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; CHECK-LABEL: catch:
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; CHECK-NEXT: load
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; Check that other adds are not hoisted
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; CHECK-LABEL: lpad4:
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; CHECK: %bc5 = add i32 %0, 10
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; CHECK-LABEL: unreachable:
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; CHECK: %bc2 = add i32 %0, 10
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; Function Attrs: noinline uwtable
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define i32 @foo2(i32* nocapture readonly %i) local_unnamed_addr personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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entry:
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%0 = load i32, i32* %i, align 4
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%cmp = icmp eq i32 %0, 0
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br i1 %cmp, label %try.cont, label %if.then
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if.then:
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%exception = tail call i8* @__cxa_allocate_exception(i64 4) #2
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%1 = bitcast i8* %exception to i32*
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store i32 %0, i32* %1, align 16
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invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
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to label %unreachable unwind label %lpad
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lpad:
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%2 = landingpad { i8*, i32 }
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catch i8* bitcast (i8** @_ZTIi to i8*)
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catch i8* null
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%bc1 = add i32 %0, 10
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%3 = extractvalue { i8*, i32 } %2, 0
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%4 = extractvalue { i8*, i32 } %2, 1
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%5 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2
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%matches = icmp eq i32 %4, %5
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%bc7 = add i32 %0, 10
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%6 = tail call i8* @__cxa_begin_catch(i8* %3) #2
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br i1 %matches, label %catch1, label %catch
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catch1:
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%bc3 = add i32 %0, 10
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invoke void @__cxa_rethrow() #3
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to label %unreachable unwind label %lpad4
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catch:
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%bc4 = add i32 %0, 10
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%7 = load i32, i32* %i, align 4
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%add = add nsw i32 %7, 1
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tail call void @__cxa_end_catch()
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br label %try.cont
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lpad4:
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%8 = landingpad { i8*, i32 }
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cleanup
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%bc5 = add i32 %0, 10
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tail call void @__cxa_end_catch() #2
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invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) #3
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to label %unreachable unwind label %lpad
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try.cont:
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%k.0 = phi i32 [ %add, %catch ], [ 0, %entry ]
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%bc6 = add i32 %0, 10
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ret i32 %k.0
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unreachable:
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%bc2 = add i32 %0, 10
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ret i32 %bc2
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}
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declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr
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declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr
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declare i32 @__gxx_personality_v0(...)
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; Function Attrs: nounwind readnone
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declare i32 @llvm.eh.typeid.for(i8*) #1
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declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
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declare void @__cxa_end_catch() local_unnamed_addr
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declare void @__cxa_rethrow() local_unnamed_addr
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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attributes #3 = { noreturn }
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