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llvm-mirror/test/MC/Mips/micromips/invalid.s

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[mips][ias] Range check uimm4 operands and fixed a bug this revealed. Summary: The bug was that the sldi instructions have immediate widths dependant on their element size. So sldi.d has a 1-bit immediate and sldi.b has a 4-bit immediate. All of these were using 4-bit immediates previously. Reviewers: vkalintiris Subscribers: llvm-commits, atanasyan, dsanders Differential Revision: http://reviews.llvm.org/D14018 llvm-svn: 252297
2015-11-06 13:41:43 +01:00
# RUN: not llvm-mc %s -triple=mips -show-encoding -mattr=micromips 2>%t1
# RUN: FileCheck %s < %t1
[mips] Range check uimm6_lsl2. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17291 llvm-svn: 263419
2016-03-14 12:16:56 +01:00
addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
[mips] Range check simm4. Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16811 llvm-svn: 263220
2016-03-11 12:37:50 +01:00
addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
[mips][ias] Range check uimm10 operands Summary: Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15229 llvm-svn: 255112
2015-12-09 14:48:05 +01:00
break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-26 17:35:41 +01:00
break16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
break16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
2015-12-21 14:08:58 +01:00
# FIXME: Check '0 < pos + size <= 32' constraint on ext
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-26 17:35:41 +01:00
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions Differential Revision: http://reviews.llvm.org/D15570 llvm-svn: 256152
2015-12-21 14:08:58 +01:00
ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
[mips][ias] Range check uimm5 operands and fix several bugs this revealed. Summary: The bugs were: * append, prepend, and balign were not tested * balign takes a uimm2 not a uimm5. * drotr32 was correctly implemented with a uimm5 but the tests expected '52' to be valid. * li/la were implemented with a uimm5 instead of simm32. simm32 isn't completely correct either but I'll fix that when I get to simm32. A notable omission are some of the shift instructions. Several of these have been implemented using a single uimm6 instruction (rather than two uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated in the uimm6 patch. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D14712 llvm-svn: 254164
2015-11-26 17:35:41 +01:00
ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
jraddiusp -1 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp -4 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 125 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
jraddiusp 128 # CHECK: :[[@LINE]]:13: error: expected both 7-bit unsigned immediate and multiple of 4
pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
sdbbp16 -1 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sdbbp16 16 # CHECK: :[[@LINE]]:11: error: expected 4-bit unsigned immediate
sll $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sll $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
sra $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
srl $2, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
[mips][microMIPS] Implement DINSU, DINSM, DINS instructions Differential Revision: http://reviews.llvm.org/D16181 llvm-svn: 261860
2016-02-25 13:53:29 +01:00
ins $2, $3, -1, 1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
ins $2, $3, 0, -1 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
ins $2, $3, 0, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
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