2011-04-07 21:54:57 +02:00
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; RUN: llc < %s -mcpu=cortex-a8 | FileCheck %s
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; Tests preRAsched support for VRegCycle interference.
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32"
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target triple = "thumbv7-apple-darwin10"
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define void @t(i32 %src_width, float* nocapture %src_copy_start, float* nocapture %dst_copy_start, i32 %src_copy_start_index) nounwind optsize {
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entry:
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%src_copy_start6 = bitcast float* %src_copy_start to i8*
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%0 = icmp eq i32 %src_width, 0
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br i1 %0, label %return, label %bb
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; Make sure the scheduler schedules all uses of the preincrement
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; induction variable before defining the postincrement value.
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; CHECK: t:
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2011-05-04 00:31:21 +02:00
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; CHECK: %bb
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2011-04-07 21:54:57 +02:00
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; CHECK-NOT: mov
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bb: ; preds = %entry, %bb
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%j.05 = phi i32 [ %2, %bb ], [ 0, %entry ]
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%tmp = mul i32 %j.05, %src_copy_start_index
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%uglygep = getelementptr i8* %src_copy_start6, i32 %tmp
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%src_copy_start_addr.04 = bitcast i8* %uglygep to float*
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%dst_copy_start_addr.03 = getelementptr float* %dst_copy_start, i32 %j.05
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%1 = load float* %src_copy_start_addr.04, align 4
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store float %1, float* %dst_copy_start_addr.03, align 4
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%2 = add i32 %j.05, 1
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%exitcond = icmp eq i32 %2, %src_width
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br i1 %exitcond, label %return, label %bb
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return: ; preds = %bb, %entry
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ret void
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}
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