2016-04-06 01:34:59 +02:00
|
|
|
//===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
|
|
|
|
//
|
2019-01-19 09:50:56 +01:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2016-04-06 01:34:59 +02:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// \file
|
|
|
|
/// This file declares the targeting of the RegisterBankInfo class for AArch64.
|
|
|
|
/// \todo This should be generated by TableGen.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
|
|
|
|
#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
|
|
|
|
|
|
|
|
#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
|
|
|
|
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
#define GET_REGBANK_DECLARATIONS
|
|
|
|
#include "AArch64GenRegisterBank.inc"
|
|
|
|
|
2016-04-06 01:34:59 +02:00
|
|
|
namespace llvm {
|
|
|
|
|
|
|
|
class TargetRegisterInfo;
|
|
|
|
|
2017-01-13 11:53:57 +01:00
|
|
|
class AArch64GenRegisterBankInfo : public RegisterBankInfo {
|
|
|
|
protected:
|
|
|
|
enum PartialMappingIdx {
|
|
|
|
PMI_None = -1,
|
2017-11-03 00:38:13 +01:00
|
|
|
PMI_FPR16 = 1,
|
|
|
|
PMI_FPR32,
|
2017-01-13 11:53:57 +01:00
|
|
|
PMI_FPR64,
|
|
|
|
PMI_FPR128,
|
|
|
|
PMI_FPR256,
|
|
|
|
PMI_FPR512,
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
PMI_GPR32,
|
|
|
|
PMI_GPR64,
|
2017-01-13 11:53:57 +01:00
|
|
|
PMI_FirstGPR = PMI_GPR32,
|
|
|
|
PMI_LastGPR = PMI_GPR64,
|
2017-11-03 00:38:13 +01:00
|
|
|
PMI_FirstFPR = PMI_FPR16,
|
2017-01-13 11:53:57 +01:00
|
|
|
PMI_LastFPR = PMI_FPR512,
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
PMI_Min = PMI_FirstFPR,
|
2017-01-13 11:53:57 +01:00
|
|
|
};
|
|
|
|
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
static RegisterBankInfo::PartialMapping PartMappings[];
|
|
|
|
static RegisterBankInfo::ValueMapping ValMappings[];
|
|
|
|
static PartialMappingIdx BankIDToCopyMapIdx[];
|
|
|
|
|
2017-01-13 11:53:57 +01:00
|
|
|
enum ValueMappingIdx {
|
2017-02-06 22:57:06 +01:00
|
|
|
InvalidIdx = 0,
|
|
|
|
First3OpsIdx = 1,
|
2017-11-03 00:38:13 +01:00
|
|
|
Last3OpsIdx = 22,
|
2017-01-13 11:53:57 +01:00
|
|
|
DistanceBetweenRegBanks = 3,
|
2017-11-03 00:38:13 +01:00
|
|
|
FirstCrossRegCpyIdx = 25,
|
|
|
|
LastCrossRegCpyIdx = 39,
|
2017-11-03 00:38:19 +01:00
|
|
|
DistanceBetweenCrossRegCpy = 2,
|
|
|
|
FPExt16To32Idx = 41,
|
|
|
|
FPExt16To64Idx = 43,
|
|
|
|
FPExt32To64Idx = 45,
|
|
|
|
FPExt64To128Idx = 47,
|
2017-01-13 11:53:57 +01:00
|
|
|
};
|
|
|
|
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
|
|
|
|
unsigned ValLength, const RegisterBank &RB);
|
|
|
|
static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
|
|
|
|
unsigned Size, unsigned Offset);
|
2017-01-13 11:53:57 +01:00
|
|
|
static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
|
|
|
|
PartialMappingIdx LastAlias,
|
2017-01-13 12:50:34 +01:00
|
|
|
ArrayRef<PartialMappingIdx> Order);
|
2017-01-13 11:53:57 +01:00
|
|
|
|
2017-01-13 12:50:34 +01:00
|
|
|
static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
|
2017-01-13 11:53:57 +01:00
|
|
|
|
2017-01-13 12:50:34 +01:00
|
|
|
/// Get the pointer to the ValueMapping representing the RegisterBank
|
|
|
|
/// at \p RBIdx with a size of \p Size.
|
|
|
|
///
|
|
|
|
/// The returned mapping works for instructions with the same kind of
|
|
|
|
/// operands for up to 3 operands.
|
|
|
|
///
|
|
|
|
/// \pre \p RBIdx != PartialMappingIdx::None
|
|
|
|
static const RegisterBankInfo::ValueMapping *
|
|
|
|
getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
|
|
|
|
|
|
|
|
/// Get the pointer to the ValueMapping of the operands of a copy
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
/// instruction from the \p SrcBankID register bank to the \p DstBankID
|
|
|
|
/// register bank with a size of \p Size.
|
2017-01-13 12:50:34 +01:00
|
|
|
static const RegisterBankInfo::ValueMapping *
|
[globalisel][aarch64] Make getCopyMapping() take register banks ID's rather than IsGPR booleans
Summary:
This allows the function to handle architectures with more than two register banks.
Depends on D27978
Reviewers: ab, t.p.northover, rovka, qcolombet
Subscribers: aditya_nandakumar, kristof.beyls, aemerson, rengolin, vkalintiris, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27339
llvm-svn: 291902
2017-01-13 15:16:33 +01:00
|
|
|
getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
|
2017-11-03 00:38:19 +01:00
|
|
|
/// Get the instruction mapping for G_FPEXT.
|
|
|
|
///
|
|
|
|
/// \pre (DstSize, SrcSize) pair is one of the following:
|
|
|
|
/// (32, 16), (64, 16), (64, 32), (128, 64)
|
|
|
|
///
|
|
|
|
/// \return An InstructionMapping with statically allocated OperandsMapping.
|
|
|
|
static const RegisterBankInfo::ValueMapping *
|
|
|
|
getFPExtMapping(unsigned DstSize, unsigned SrcSize);
|
|
|
|
|
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Summary:
Adds a RegisterBank tablegen class that can be used to declare the register
banks and an associated tablegen pass to generate the necessary code.
Changes since first commit attempt:
* Added missing guards
* Added more missing guards
* Found and fixed a use-after-free bug involving Twine locals
Reviewers: t.p.northover, ab, rovka, qcolombet
Reviewed By: qcolombet
Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka
Differential Revision: https://reviews.llvm.org/D27338
llvm-svn: 292478
2017-01-19 12:15:55 +01:00
|
|
|
#define GET_TARGET_REGBANK_CLASS
|
|
|
|
#include "AArch64GenRegisterBank.inc"
|
2017-01-13 11:53:57 +01:00
|
|
|
};
|
|
|
|
|
2016-04-06 01:34:59 +02:00
|
|
|
/// This class provides the information for the target register banks.
|
2017-01-13 11:53:57 +01:00
|
|
|
class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
|
2016-06-08 18:53:32 +02:00
|
|
|
/// See RegisterBankInfo::applyMapping.
|
|
|
|
void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
|
|
|
|
|
2016-10-03 22:20:13 +02:00
|
|
|
/// Get an instruction mapping where all the operands map to
|
|
|
|
/// the same register bank and have similar size.
|
|
|
|
///
|
|
|
|
/// \pre MI.getNumOperands() <= 3
|
|
|
|
///
|
|
|
|
/// \return An InstructionMappings with a statically allocated
|
|
|
|
/// OperandsMapping.
|
2017-05-06 00:48:22 +02:00
|
|
|
const InstructionMapping &
|
|
|
|
getSameKindOfOperandsMapping(const MachineInstr &MI) const;
|
2016-10-03 22:20:13 +02:00
|
|
|
|
2016-04-06 01:34:59 +02:00
|
|
|
public:
|
|
|
|
AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
|
2016-12-15 19:22:15 +01:00
|
|
|
|
2016-06-08 03:11:03 +02:00
|
|
|
unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
|
|
|
|
unsigned Size) const override;
|
2016-04-07 02:14:30 +02:00
|
|
|
|
|
|
|
const RegisterBank &
|
|
|
|
getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
|
2016-06-08 18:53:32 +02:00
|
|
|
|
|
|
|
InstructionMappings
|
|
|
|
getInstrAlternativeMappings(const MachineInstr &MI) const override;
|
2016-07-20 21:09:30 +02:00
|
|
|
|
2017-05-06 00:48:22 +02:00
|
|
|
const InstructionMapping &
|
|
|
|
getInstrMapping(const MachineInstr &MI) const override;
|
2016-04-06 01:34:59 +02:00
|
|
|
};
|
|
|
|
} // End llvm namespace.
|
|
|
|
#endif
|