llvm-mirror/test/CodeGen/Mips/small-section-reserve-gp.ll

; RUN: llc -mtriple=mipsel-sde-elf -march=mipsel -relocation-model=static -mattr=+noabicalls -mgpopt < %s \
; RUN: | FileCheck %s

@i = internal unnamed_addr global i32 0, align 4

define i32 @geti() nounwind readonly {
entry:
; CHECK: lw ${{[0-9]+}}, %gp_rel(i)($gp)
  %0 = load i32, i32* @i, align 4
  ret i32 %0
}
[mips] Add the following MIPS options that control gp-relative addressing of small data items: -mgpopt, -mlocal-sdata, -mextern-sdata. Implement gp-relative addressing for constants. Differential Revision: http://reviews.llvm.org/D4903 llvm-svn: 221450 2014-11-06 14:20:12 +01:00			`; RUN: llc -mtriple=mipsel-sde-elf -march=mipsel -relocation-model=static -mattr=+noabicalls -mgpopt < %s \`
Add register Mips::GP to the list of reserved registers if target is bare-metal to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340 2012-08-22 05:18:13 +02:00			`; RUN: \| FileCheck %s`

			`@i = internal unnamed_addr global i32 0, align 4`

			`define i32 @geti() nounwind readonly {`
			`entry:`
In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its second operand is MipsISD::GPRel. llvm-svn: 162584 2012-08-24 22:21:49 +02:00			`; CHECK: lw ${{[0-9]+}}, %gp_rel(i)($gp)`
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=\|:\|^)\sload (?:atomic )?(?:volatile )?(.?))(\| addrspace\(\d+\) )\($\| (?:%\|@\|null\|undef\|blockaddress\|getelementptr\|addrspacecast\|bitcast\|inttoptr\|\[\[[a-zA-Z]\|\{\{).$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 2015-02-27 22:17:42 +01:00			`%0 = load i32, i32* @i, align 4`
Add register Mips::GP to the list of reserved registers if target is bare-metal to prevent it from being clobbered. mips uses $gp to access small data section. This bug was originally reported by Carl Norum. llvm-svn: 162340 2012-08-22 05:18:13 +02:00			`ret i32 %0`
			`}`