llvm-mirror/test/CodeGen/Hexagon/struct_args_large.ll

; RUN: true
; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)
; CHECK: r[[T1:[0-9]+]] = memw(r[[T0]] + #0)
; CHECK: memw(r29 + #0) = r[[T1]]

%struct.large = type { i64, i64 }

@s2 = common global %struct.large zeroinitializer, align 8

define void @foo() nounwind {
entry:
  call void @bar(%struct.large* byval @s2)
  ret void
}

declare void @bar(%struct.large* byval)
Disable Hexagon test temporarily. There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617 2012-04-12 23:06:54 +02:00			`; RUN: true`
			`; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s \| FileCheck %s`
Hexagon backend support llvm-svn: 146412 2011-12-12 22:14:40 +01:00			`; CHECK: r[[T0:[0-9]+]] = CONST32(#s2)`
			`; CHECK: r[[T1:[0-9]+]] = memw(r[[T0]] + #0)`
			`; CHECK: memw(r29 + #0) = r[[T1]]`

			`%struct.large = type { i64, i64 }`

			`@s2 = common global %struct.large zeroinitializer, align 8`

			`define void @foo() nounwind {`
			`entry:`
			`call void @bar(%struct.large* byval @s2)`
			`ret void`
			`}`

			`declare void @bar(%struct.large* byval)`