2012-02-18 13:03:15 +01:00
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//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-29 21:36:04 +01:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 01:30:14 +02:00
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//
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2004-08-17 06:55:41 +02:00
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//===----------------------------------------------------------------------===//
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//
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2008-02-10 19:45:23 +01:00
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// This file contains the PowerPC implementation of the TargetRegisterInfo
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// class.
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2004-08-17 06:55:41 +02:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef POWERPC32_REGISTERINFO_H
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#define POWERPC32_REGISTERINFO_H
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2005-10-15 01:51:18 +02:00
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#include "PPC.h"
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2014-01-07 12:48:04 +01:00
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#include "llvm/ADT/DenseMap.h"
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2004-08-17 06:55:41 +02:00
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2011-06-27 20:32:37 +02:00
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#define GET_REGINFO_HEADER
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#include "PPCGenRegisterInfo.inc"
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2004-08-17 06:55:41 +02:00
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namespace llvm {
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2006-07-11 02:48:23 +02:00
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class PPCSubtarget;
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2006-11-28 00:37:22 +01:00
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class TargetInstrInfo;
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2004-08-17 06:55:41 +02:00
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class Type;
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2005-10-16 07:39:50 +02:00
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class PPCRegisterInfo : public PPCGenRegisterInfo {
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2013-03-31 16:43:31 +02:00
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DenseMap<unsigned, unsigned> ImmToIdxMap;
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const PPCSubtarget &Subtarget;
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public:
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PPCRegisterInfo(const PPCSubtarget &SubTarget);
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2006-04-17 23:07:20 +02:00
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2009-02-06 18:43:24 +01:00
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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2014-04-29 09:57:37 +02:00
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
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2009-02-06 18:43:24 +01:00
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2011-11-22 17:21:04 +01:00
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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2011-11-22 17:21:04 +01:00
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2014-03-29 06:29:01 +01:00
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
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2014-03-29 06:29:01 +01:00
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2004-08-17 06:55:41 +02:00
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/// Code Generation virtual methods...
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2014-04-29 09:57:37 +02:00
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const MCPhysReg *
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getCalleeSavedRegs(const MachineFunction* MF =nullptr) const override;
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const uint32_t *getCallPreservedMask(CallingConv::ID CC) const override;
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2013-03-21 22:37:52 +01:00
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const uint32_t *getNoPreservedMask() const;
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2006-05-18 02:12:58 +02:00
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2014-04-29 09:57:37 +02:00
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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2007-02-19 22:49:54 +01:00
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2013-03-14 21:21:47 +01:00
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/// We require the register scavenger.
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bool requiresRegisterScavenging(const MachineFunction &MF) const override {
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2013-03-12 15:12:16 +01:00
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return true;
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}
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2008-03-03 23:19:16 +01:00
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2014-04-29 09:57:37 +02:00
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
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return true;
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}
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2014-04-29 09:57:37 +02:00
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
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return true;
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}
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2012-04-23 23:39:35 +02:00
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2014-04-29 09:57:37 +02:00
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bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
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2013-04-09 19:27:09 +02:00
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return true;
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}
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2013-03-23 20:36:47 +01:00
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void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
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void lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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Add CR-bit tracking to the PowerPC backend for i1 values
This change enables tracking i1 values in the PowerPC backend using the
condition register bits. These bits can be treated on PowerPC as separate
registers; individual bit operations (and, or, xor, etc.) are supported.
Tracking booleans in CR bits has several advantages:
- Reduction in register pressure (because we no longer need GPRs to store
boolean values).
- Logical operations on booleans can be handled more efficiently; we used to
have to move all results from comparisons into GPRs, perform promoted
logical operations in GPRs, and then move the result back into condition
register bits to be used by conditional branches. This can be very
inefficient, because the throughput of these CR <-> GPR moves have high
latency and low throughput (especially when other associated instructions
are accounted for).
- On the POWER7 and similar cores, we can increase total throughput by using
the CR bits. CR bit operations have a dedicated functional unit.
Most of this is more-or-less mechanical: Adjustments were needed in the
calling-convention code, support was added for spilling/restoring individual
condition-register bits, and conditional branch instruction definitions taking
specific CR bits were added (plus patterns and code for generating bit-level
operations).
This is enabled by default when running at -O2 and higher. For -O0 and -O1,
where the ability to debug is more important, this feature is disabled by
default. Individual CR bits do not have assigned DWARF register numbers,
and storing values in CR bits makes them invisible to the debugger.
It is critical, however, that we don't move i1 values that have been promoted
to larger values (such as those passed as function arguments) into bit
registers only to quickly turn around and move the values back into GPRs (such
as happens when values are returned by functions). A pair of target-specific
DAG combines are added to remove the trunc/extends in:
trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
and:
zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
In short, we only want to use CR bits where some of the i1 values come from
comparisons or are used by conditional branches or selects. To put it another
way, if we can do the entire i1 computation in GPRs, then we probably should
(on the POWER7, the GPR-operation throughput is higher, and for all cores, the
CR <-> GPR moves are expensive).
POWER7 test-suite performance results (from 10 runs in each configuration):
SingleSource/Benchmarks/Misc/mandel-2: 35% speedup
MultiSource/Benchmarks/Prolangs-C++/city/city: 21% speedup
MultiSource/Benchmarks/MiBench/automotive-susan: 23% speedup
SingleSource/Benchmarks/CoyoteBench/huffbench: 13% speedup
SingleSource/Benchmarks/Misc-C++/Large/sphereflake: 13% speedup
SingleSource/Benchmarks/Misc-C++/mandel-text: 10% speedup
SingleSource/Benchmarks/Misc-C++-EH/spirit: 10% slowdown
MultiSource/Applications/lemon/lemon: 8% slowdown
llvm-svn: 202451
2014-02-28 01:27:01 +01:00
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void lowerCRBitSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRBitRestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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2013-03-23 20:36:47 +01:00
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void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerVRSAVERestore(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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2013-03-21 20:03:21 +01:00
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2012-09-12 16:47:47 +02:00
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bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
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int &FrameIdx) const override;
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2010-08-27 01:32:16 +02:00
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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2013-01-31 21:02:54 +01:00
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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2004-08-17 06:55:41 +02:00
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2013-04-09 19:27:09 +02:00
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// Support for virtual base registers.
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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2013-04-09 19:27:09 +02:00
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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2014-04-02 21:28:18 +02:00
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI,
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int64_t Offset) const override;
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2013-04-09 19:27:09 +02:00
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2006-03-28 15:48:33 +02:00
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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2007-02-21 23:54:50 +01:00
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2013-07-17 02:45:52 +02:00
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// Base pointer (stack realignment) support.
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unsigned getBaseRegister(const MachineFunction &MF) const;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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2014-04-29 09:57:37 +02:00
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bool needsStackRealignment(const MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif
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