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llvm-mirror/test/Bitcode/neon-intrinsics.ll

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Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and zero-extend operations. llvm-svn: 111614
2010-08-20 06:54:02 +02:00
; RUN: llvm-dis < %s.bc | FileCheck %s
; vmovls should be auto-upgraded to sext
; CHECK: vmovls8
; CHECK-NOT: arm.neon.vmovls.v8i16
; CHECK: sext <8 x i8>
; CHECK: vmovls16
; CHECK-NOT: arm.neon.vmovls.v4i32
; CHECK: sext <4 x i16>
; CHECK: vmovls32
; CHECK-NOT: arm.neon.vmovls.v2i64
; CHECK: sext <2 x i32>
; vmovlu should be auto-upgraded to zext
; CHECK: vmovlu8
; CHECK-NOT: arm.neon.vmovlu.v8i16
; CHECK: zext <8 x i8>
; CHECK: vmovlu16
; CHECK-NOT: arm.neon.vmovlu.v4i32
; CHECK: zext <4 x i16>
; CHECK: vmovlu32
; CHECK-NOT: arm.neon.vmovlu.v2i64
; CHECK: zext <2 x i32>
Add alignment arguments to all the NEON load/store intrinsics. Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. llvm-svn: 112271
2010-08-27 19:13:24 +02:00
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. llvm-svn: 112416
2010-08-29 07:57:34 +02:00
; vaddl/vaddw should be auto-upgraded to add with sext/zext
; CHECK: vaddls16
; CHECK-NOT: arm.neon.vaddls.v4i32
; CHECK: sext <4 x i16>
; CHECK-NEXT: sext <4 x i16>
; CHECK-NEXT: add <4 x i32>
; CHECK: vaddlu32
; CHECK-NOT: arm.neon.vaddlu.v2i64
; CHECK: zext <2 x i32>
; CHECK-NEXT: zext <2 x i32>
; CHECK-NEXT: add <2 x i64>
; CHECK: vaddws8
; CHECK-NOT: arm.neon.vaddws.v8i16
; CHECK: sext <8 x i8>
; CHECK-NEXT: add <8 x i16>
; CHECK: vaddwu16
; CHECK-NOT: arm.neon.vaddwu.v4i32
; CHECK: zext <4 x i16>
; CHECK-NEXT: add <4 x i32>
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. llvm-svn: 112773
2010-09-02 01:50:19 +02:00
; vsubl/vsubw should be auto-upgraded to subtract with sext/zext
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm IR add/sub operations with one or both operands sign- or zero-extended. Auto-upgrade the old intrinsics. llvm-svn: 112416
2010-08-29 07:57:34 +02:00
; CHECK: vsubls16
; CHECK-NOT: arm.neon.vsubls.v4i32
; CHECK: sext <4 x i16>
; CHECK-NEXT: sext <4 x i16>
; CHECK-NEXT: sub <4 x i32>
; CHECK: vsublu32
; CHECK-NOT: arm.neon.vsublu.v2i64
; CHECK: zext <2 x i32>
; CHECK-NEXT: zext <2 x i32>
; CHECK-NEXT: sub <2 x i64>
; CHECK: vsubws8
; CHECK-NOT: arm.neon.vsubws.v8i16
; CHECK: sext <8 x i8>
; CHECK-NEXT: sub <8 x i16>
; CHECK: vsubwu16
; CHECK-NOT: arm.neon.vsubwu.v4i32
; CHECK: zext <4 x i16>
; CHECK-NEXT: sub <4 x i32>
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, add, and subtract operations with zero-extended or sign-extended vectors. Update tests. Add auto-upgrade support for the old intrinsics. llvm-svn: 112773
2010-09-02 01:50:19 +02:00
; vmull should be auto-upgraded to multiply with sext/zext
; (but vmullp should remain an intrinsic)
; CHECK: vmulls8
; CHECK-NOT: arm.neon.vmulls.v8i16
; CHECK: sext <8 x i8>
; CHECK-NEXT: sext <8 x i8>
; CHECK-NEXT: mul <8 x i16>
; CHECK: vmullu16
; CHECK-NOT: arm.neon.vmullu.v4i32
; CHECK: zext <4 x i16>
; CHECK-NEXT: zext <4 x i16>
; CHECK-NEXT: mul <4 x i32>
; CHECK: vmullp8
; CHECK: arm.neon.vmullp.v8i16
; vmlal should be auto-upgraded to multiply/add with sext/zext
; CHECK: vmlals32
; CHECK-NOT: arm.neon.vmlals.v2i64
; CHECK: sext <2 x i32>
; CHECK-NEXT: sext <2 x i32>
; CHECK-NEXT: mul <2 x i64>
; CHECK-NEXT: add <2 x i64>
; CHECK: vmlalu8
; CHECK-NOT: arm.neon.vmlalu.v8i16
; CHECK: zext <8 x i8>
; CHECK-NEXT: zext <8 x i8>
; CHECK-NEXT: mul <8 x i16>
; CHECK-NEXT: add <8 x i16>
; vmlsl should be auto-upgraded to multiply/sub with sext/zext
; CHECK: vmlsls16
; CHECK-NOT: arm.neon.vmlsls.v4i32
; CHECK: sext <4 x i16>
; CHECK-NEXT: sext <4 x i16>
; CHECK-NEXT: mul <4 x i32>
; CHECK-NEXT: sub <4 x i32>
; CHECK: vmlslu32
; CHECK-NOT: arm.neon.vmlslu.v2i64
; CHECK: zext <2 x i32>
; CHECK-NEXT: zext <2 x i32>
; CHECK-NEXT: mul <2 x i64>
; CHECK-NEXT: sub <2 x i64>
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. llvm-svn: 112941
2010-09-03 03:35:08 +02:00
; vaba should be auto-upgraded to vabd + add
; CHECK: vabas32
; CHECK-NOT: arm.neon.vabas.v2i32
; CHECK: arm.neon.vabds.v2i32
; CHECK-NEXT: add <2 x i32>
; CHECK: vabaQu8
; CHECK-NOT: arm.neon.vabau.v16i8
; CHECK: arm.neon.vabdu.v16i8
; CHECK-NEXT: add <16 x i8>
; vabal should be auto-upgraded to vabd with zext + add
; CHECK: vabals16
; CHECK-NOT: arm.neon.vabals.v4i32
; CHECK: arm.neon.vabds.v4i16
; CHECK-NEXT: zext <4 x i16>
; CHECK-NEXT: add <4 x i32>
; CHECK: vabalu32
; CHECK-NOT: arm.neon.vabalu.v2i64
; CHECK: arm.neon.vabdu.v2i32
; CHECK-NEXT: zext <2 x i32>
; CHECK-NEXT: add <2 x i64>
; vabdl should be auto-upgraded to vabd with zext
; CHECK: vabdls8
; CHECK-NOT: arm.neon.vabdls.v8i16
; CHECK: arm.neon.vabds.v8i8
; CHECK-NEXT: zext <8 x i8>
; CHECK: vabdlu16
; CHECK-NOT: arm.neon.vabdlu.v4i32
; CHECK: arm.neon.vabdu.v4i16
; CHECK-NEXT: zext <4 x i16>
Remove NEON vmovn intrinsic, replacing it with vector truncate operations. Auto-upgrade the old intrinsic and update tests. llvm-svn: 112507
2010-08-30 22:02:30 +02:00
; vmovn should be auto-upgraded to trunc
; CHECK: vmovni16
; CHECK-NOT: arm.neon.vmovn.v8i8
; CHECK: trunc <8 x i16>
; CHECK: vmovni32
; CHECK-NOT: arm.neon.vmovn.v4i16
; CHECK: trunc <4 x i32>
; CHECK: vmovni64
; CHECK-NOT: arm.neon.vmovn.v2i32
; CHECK: trunc <2 x i64>
Add alignment arguments to all the NEON load/store intrinsics. Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. llvm-svn: 112271
2010-08-27 19:13:24 +02:00
; vld* and vst* intrinsic calls need an alignment argument (defaulted to 1)
; CHECK: vld1i8
; CHECK: i32 1
; CHECK: vld2Qi16
; CHECK: i32 1
; CHECK: vld3i32
; CHECK: i32 1
; CHECK: vld4Qf
; CHECK: i32 1
; CHECK: vst1i8
; CHECK: i32 1
; CHECK: vst2Qi16
; CHECK: i32 1
; CHECK: vst3i32
; CHECK: i32 1
; CHECK: vst4Qf
; CHECK: i32 1
; CHECK: vld2laneQi16
; CHECK: i32 1
; CHECK: vld3lanei32
; CHECK: i32 1
; CHECK: vld4laneQf
; CHECK: i32 1
; CHECK: vst2laneQi16
; CHECK: i32 1
; CHECK: vst3lanei32
; CHECK: i32 1
; CHECK: vst4laneQf
; CHECK: i32 1
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