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https://github.com/RPCS3/llvm-mirror.git
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54 lines
2.5 KiB
LLVM
54 lines
2.5 KiB
LLVM
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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;
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; Check that this does not crash.
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target triple = "hexagon"
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; CHECK-LABEL: danny:
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; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
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; CHECK-DAG: if (![[PREG]]) [[VREG]]
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define void @danny() local_unnamed_addr #0 {
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b0:
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%v1 = icmp eq i32 0, undef
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%v2 = select i1 %v1, <16 x i32> zeroinitializer, <16 x i32> undef
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%v3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v2, <16 x i32> zeroinitializer, i32 2)
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%v4 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %v3)
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%v5 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v4)
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%v6 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %v5, i32 62)
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%v7 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v6)
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store <16 x i32> %v7, <16 x i32>* undef, align 64
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unreachable
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}
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #2
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declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #2
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #2
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #2
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declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #2
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; CHECK-LABEL: sammy:
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; CHECK-DAG: if ([[PREG:p[0-3]]]) [[VREG:v[0-9]+]]
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; CHECK-DAG: if (![[PREG]]) [[VREG]]
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define void @sammy() local_unnamed_addr #1 {
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b0:
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%v1 = icmp eq i32 0, undef
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%v2 = select i1 %v1, <32 x i32> zeroinitializer, <32 x i32> undef
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%v3 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %v2, <32 x i32> zeroinitializer, i32 2)
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%v4 = tail call <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1> undef, <32 x i32> undef, <32 x i32> %v3)
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%v5 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v4)
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%v6 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %v5, i32 62)
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%v7 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v6)
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store <32 x i32> %v7, <32 x i32>* undef, align 128
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unreachable
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}
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declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #2
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declare <64 x i32> @llvm.hexagon.V6.vswap.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #2
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2
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declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
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attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" }
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attributes #2 = { nounwind readnone }
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