llvm-mirror/test/CodeGen/X86/fastcc.ll

; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false | FileCheck %s
; CHECK: movsd %xmm{{[0-9]}}, 8(%esp)
; CHECK: xorl %eax, %eax

@d = external global double		; <double*> [#uses=1]
@c = external global double		; <double*> [#uses=1]
@b = external global double		; <double*> [#uses=1]
@a = external global double		; <double*> [#uses=1]

define i32 @foo() nounwind {
entry:
	%0 = load double* @d, align 8		; <double> [#uses=1]
	%1 = load double* @c, align 8		; <double> [#uses=1]
	%2 = load double* @b, align 8		; <double> [#uses=1]
	%3 = load double* @a, align 8		; <double> [#uses=1]
	tail call fastcc void @bar( i32 0, i32 1, i32 2, double 1.000000e+00, double %3, double %2, double %1, double %0 ) nounwind
	ret i32 0
}

declare fastcc void @bar(i32, i32, i32, double, double, double, double, double)
Turn on post-alloc scheduling for x86. llvm-svn: 84431 2009-10-18 21:57:27 +02:00			`; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -post-RA-scheduler=false \| FileCheck %s`
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750 2013-10-16 01:33:07 +02:00			`; CHECK: movsd %xmm{{[0-9]}}, 8(%esp)`
			`; CHECK: xorl %eax, %eax`
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. llvm-svn: 55807 2008-09-05 00:59:58 +02:00
			`@d = external global double ; <double*> [#uses=1]`
			`@c = external global double ; <double*> [#uses=1]`
			`@b = external global double ; <double*> [#uses=1]`
			`@a = external global double ; <double*> [#uses=1]`

			`define i32 @foo() nounwind {`
			`entry:`
			`%0 = load double* @d, align 8 ; <double> [#uses=1]`
			`%1 = load double* @c, align 8 ; <double> [#uses=1]`
			`%2 = load double* @b, align 8 ; <double> [#uses=1]`
			`%3 = load double* @a, align 8 ; <double> [#uses=1]`
			`tail call fastcc void @bar( i32 0, i32 1, i32 2, double 1.000000e+00, double %3, double %2, double %1, double %0 ) nounwind`
			`ret i32 0`
			`}`

			`declare fastcc void @bar(i32, i32, i32, double, double, double, double, double)`