RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
Code Issues Projects Releases Wiki Activity
a5a991435e
llvm-mirror/test/CodeGen/PowerPC/float-load-store-pair.ll

103 lines
4.4 KiB
LLVM
Raw Normal View History

[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mcpu=pwr9 -mtriple=powerpc64le-ibm-linux| FileCheck %s
; This file verifies that for a given floating point load / store pair,
; if the load value isn't used by any other operations,
; then consider transforming the pair to integer load / store operations
@a1 = local_unnamed_addr global double 0.000000e+00, align 8
@a2 = local_unnamed_addr global double 0.000000e+00, align 8
@a3 = local_unnamed_addr global double 0.000000e+00, align 8
@a4 = local_unnamed_addr global double 0.000000e+00, align 8
@a5 = local_unnamed_addr global double 0.000000e+00, align 8
@a6 = local_unnamed_addr global double 0.000000e+00, align 8
@a7 = local_unnamed_addr global double 0.000000e+00, align 8
@a8 = local_unnamed_addr global double 0.000000e+00, align 8
@a9 = local_unnamed_addr global double 0.000000e+00, align 8
@a10 = local_unnamed_addr global double 0.000000e+00, align 8
@a11 = local_unnamed_addr global double 0.000000e+00, align 8
@a12 = local_unnamed_addr global double 0.000000e+00, align 8
@a13 = local_unnamed_addr global double 0.000000e+00, align 8
@a14 = local_unnamed_addr global double 0.000000e+00, align 8
@a15 = local_unnamed_addr global double 0.000000e+00, align 8
@a16 = local_unnamed_addr global ppc_fp128 0xM00000000000000000000000000000000, align 16
@a17 = local_unnamed_addr global fp128 0xL00000000000000000000000000000000, align 16
; Because this test function is trying to pass float argument by stack,
; so the fpr is only used to load/store float argument
[PowerPC][NFC] Avoid checking non-relevant .cfi instructions Summary: This is brought up in https://reviews.llvm.org/D64662?id=209923#inline-599490 CFI information are non-relevant to quite some testcases, we should get rid of checking them when its unecessary. This patch avoid generating cfi info in testcases that are not testing prolog/epilog or exception handling. Reviewers: kbarton, hfinkel, nemanjai, #powerpc Reviewed By: hfinkel Subscribers: MaskRay, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67016 llvm-svn: 370505
2019-08-30 21:24:25 +02:00
define signext i32 @test() nounwind {
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -192(1)
; CHECK-NEXT: addis 3, 2, a1@toc@ha
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
2020-01-07 16:43:46 +01:00
; CHECK-NEXT: addis 5, 2, a16@toc@ha
; CHECK-NEXT: addis 6, 2, a17@toc@ha
; CHECK-NEXT: addis 4, 2, a15@toc@ha
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-NEXT: lfd 1, a1@toc@l(3)
; CHECK-NEXT: addis 3, 2, a2@toc@ha
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
2020-01-07 16:43:46 +01:00
; CHECK-NEXT: addi 5, 5, a16@toc@l
; CHECK-NEXT: addi 6, 6, a17@toc@l
; CHECK-NEXT: ld 4, a15@toc@l(4)
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-NEXT: lfd 2, a2@toc@l(3)
; CHECK-NEXT: addis 3, 2, a3@toc@ha
[MachineScheduler] Fix the TopDepth/BotHeightReduce latency heuristics tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
2020-01-07 16:43:46 +01:00
; CHECK-NEXT: lxvx 34, 0, 6
; CHECK-NEXT: lxvx 0, 0, 5
; CHECK-NEXT: li 5, 152
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-NEXT: lfd 3, a3@toc@l(3)
; CHECK-NEXT: addis 3, 2, a4@toc@ha
; CHECK-NEXT: lfd 4, a4@toc@l(3)
; CHECK-NEXT: addis 3, 2, a5@toc@ha
; CHECK-NEXT: lfd 5, a5@toc@l(3)
; CHECK-NEXT: addis 3, 2, a6@toc@ha
; CHECK-NEXT: lfd 6, a6@toc@l(3)
; CHECK-NEXT: addis 3, 2, a7@toc@ha
; CHECK-NEXT: lfd 7, a7@toc@l(3)
; CHECK-NEXT: addis 3, 2, a8@toc@ha
; CHECK-NEXT: lfd 8, a8@toc@l(3)
; CHECK-NEXT: addis 3, 2, a9@toc@ha
; CHECK-NEXT: lfd 9, a9@toc@l(3)
; CHECK-NEXT: addis 3, 2, a10@toc@ha
; CHECK-NEXT: lfd 10, a10@toc@l(3)
; CHECK-NEXT: addis 3, 2, a11@toc@ha
[PowerPC] Enable default support of quad precision operations Summary: Remove option guarding support of quad precision operations. Reviewers: nemanjai, #powerpc, steven.zhang Reviewed By: nemanjai, #powerpc, steven.zhang Subscribers: qiucf, wuzish, nemanjai, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D83437
2020-07-09 00:07:34 +02:00
; CHECK-NEXT: lfd 11, a11@toc@l(3)
; CHECK-NEXT: addis 3, 2, a12@toc@ha
; CHECK-NEXT: lfd 12, a12@toc@l(3)
; CHECK-NEXT: addis 3, 2, a13@toc@ha
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-NEXT: lfd 13, a13@toc@l(3)
; CHECK-NEXT: addis 3, 2, a14@toc@ha
[PowerPC] Replace float load/store pair with integer load/store pair when it's only used in load/store Replace float load/store pair with integer load/store pair when it's only used in load/store, because float load/store instructions cost more cycles then integer load/store. A typical scenario is when there is a call with more than 13 float arguments passing, we need pass them by stack. So we need a load/store pair to do such memory operation if the variable is global variable. Differential Revision: https://reviews.llvm.org/D64195 llvm-svn: 366775
2019-07-23 05:34:40 +02:00
; CHECK-NEXT: ld 3, a14@toc@l(3)
; CHECK-NEXT: stxvx 0, 1, 5
; CHECK-NEXT: std 4, 144(1)
; CHECK-NEXT: std 3, 136(1)
[NFC][PowerPC] Add test case for D64195 llvm-svn: 366191
2019-07-16 09:54:47 +02:00
; CHECK-NEXT: bl _Z3fooddddddddddddddd
; CHECK-NEXT: nop
; CHECK-NEXT: li 3, 0
; CHECK-NEXT: addi 1, 1, 192
; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
%1 = load double, double* @a1, align 8
%2 = load double, double* @a2, align 8
%3 = load double, double* @a3, align 8
%4 = load double, double* @a4, align 8
%5 = load double, double* @a5, align 8
%6 = load double, double* @a6, align 8
%7 = load double, double* @a7, align 8
%8 = load double, double* @a8, align 8
%9 = load double, double* @a9, align 8
%10 = load double, double* @a10, align 8
%11 = load double, double* @a11, align 8
%12 = load double, double* @a12, align 8
%13 = load double, double* @a13, align 8
%14 = load double, double* @a14, align 8
%15 = load double, double* @a15, align 8
%16 = load ppc_fp128, ppc_fp128* @a16, align 16
%17 = load fp128, fp128* @a17, align 16
tail call void @_Z3fooddddddddddddddd(double %1, double %2, double %3, double %4, double %5, double %6, double %7, double %8, double %9, double %10, double %11, double %12, double %13, double %14, double %15, ppc_fp128 %16, fp128 %17)
ret i32 0
}
declare void @_Z3fooddddddddddddddd(double, double, double, double, double, double, double, double, double, double, double, double, double, double, double, ppc_fp128, fp128)
Reference in New Issue Copy Permalink