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llvm-mirror/test/CodeGen/R600/trunc.ll

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R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
2013-10-10 19:11:46 +02:00
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
R600: Fix i64 to i32 trunc on SI llvm-svn: 190091
2013-09-05 21:41:10 +02:00
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
; SI-LABEL: @trunc_i64_to_i32_store
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 03:35:51 +01:00
; SI: S_LOAD_DWORD s0, s[0:1], 11
; SI: V_MOV_B32_e32 v0, s0
; SI: BUFFER_STORE_DWORD v0
R600: Fix i64 to i32 trunc on SI llvm-svn: 190091
2013-09-05 21:41:10 +02:00
; EG-LABEL: @trunc_i64_to_i32_store
; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; EG: LSHR
; EG-NEXT: 2(
%result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
R600: Fix trunc i64 to i32 on SI llvm-svn: 192375
2013-10-10 20:04:16 +02:00
; SI-LABEL: @trunc_shl_i64:
; SI: S_LOAD_DWORDX2
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 03:35:51 +01:00
; SI: S_LOAD_DWORDX2 [[SREG:s\[[0-9]+:[0-9]+\]]]
R600/SI: Prefer SALU instructions for bit shift operations All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
2013-11-14 00:36:37 +01:00
; SI: S_LSHL_B64 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, [[SREG]], 2
; SI: MOV_B32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
2013-11-12 03:35:51 +01:00
; SI: BUFFER_STORE_DWORD v[[LO_VREG]],
R600: Fix trunc i64 to i32 on SI llvm-svn: 192375
2013-10-10 20:04:16 +02:00
define void @trunc_shl_i64(i32 addrspace(1)* %out, i64 %a) {
%b = shl i64 %a, 2
%result = trunc i64 %b to i32
store i32 %result, i32 addrspace(1)* %out, align 4
ret void
}
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