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llvm-mirror/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll

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teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4), transforming it into (add (i32 GPR), 4). This allows us to write type generic multi patterns and have tblgen automatically drop the bitconvert in the case when the types align. This allows us to fold an extra load in the changed testcase. llvm-svn: 99756
2010-03-28 10:38:32 +02:00
; RUN: llc < %s -o - -march=x86 -mattr=+mmx | FileCheck %s
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
; There are no MMX instructions here. We use add+adcl for the adds.
Testcase for codegen bug. llvm-svn: 36450
2007-04-25 23:58:17 +02:00
teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4), transforming it into (add (i32 GPR), 4). This allows us to write type generic multi patterns and have tblgen automatically drop the bitconvert in the case when the types align. This allows us to fold an extra load in the changed testcase. llvm-svn: 99756
2010-03-28 10:38:32 +02:00
define <1 x i64> @unsigned_add3(<1 x i64>* %a, <1 x i64>* %b, i32 %count) nounwind {
Testcase for codegen bug. llvm-svn: 36450
2007-04-25 23:58:17 +02:00
entry:
%tmp2942 = icmp eq i32 %count, 0 ; <i1> [#uses=1]
br i1 %tmp2942, label %bb31, label %bb26
bb26: ; preds = %bb26, %entry
teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4), transforming it into (add (i32 GPR), 4). This allows us to write type generic multi patterns and have tblgen automatically drop the bitconvert in the case when the types align. This allows us to fold an extra load in the changed testcase. llvm-svn: 99756
2010-03-28 10:38:32 +02:00
Make test not sensitive to register choice. llvm-svn: 115250
2010-10-01 02:16:17 +02:00
; CHECK: addl %e
; CHECK: adcl %e
teach tblgen to allow patterns like (add (i32 (bitconvert (i32 GPR))), 4), transforming it into (add (i32 GPR), 4). This allows us to write type generic multi patterns and have tblgen automatically drop the bitconvert in the case when the types align. This allows us to fold an extra load in the changed testcase. llvm-svn: 99756
2010-03-28 10:38:32 +02:00
Testcase for codegen bug. llvm-svn: 36450
2007-04-25 23:58:17 +02:00
%i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3]
%sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1]
%tmp13 = getelementptr <1 x i64>* %b, i32 %i.037.0 ; <<1 x i64>*> [#uses=1]
%tmp14 = load <1 x i64>* %tmp13 ; <<1 x i64>> [#uses=1]
%tmp18 = getelementptr <1 x i64>* %a, i32 %i.037.0 ; <<1 x i64>*> [#uses=1]
%tmp19 = load <1 x i64>* %tmp18 ; <<1 x i64>> [#uses=1]
%tmp21 = add <1 x i64> %tmp19, %tmp14 ; <<1 x i64>> [#uses=1]
%tmp22 = add <1 x i64> %tmp21, %sum.035.0 ; <<1 x i64>> [#uses=2]
%tmp25 = add i32 %i.037.0, 1 ; <i32> [#uses=2]
%tmp29 = icmp ult i32 %tmp25, %count ; <i1> [#uses=1]
br i1 %tmp29, label %bb26, label %bb31
bb31: ; preds = %bb26, %entry
%sum.035.1 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1]
ret <1 x i64> %sum.035.1
}
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 01:57:10 +02:00
; This is the original test converted to use MMX intrinsics.
define <1 x i64> @unsigned_add3a(x86_mmx* %a, x86_mmx* %b, i32 %count) nounwind {
entry:
%tmp2943 = bitcast <1 x i64><i64 0> to x86_mmx
%tmp2942 = icmp eq i32 %count, 0 ; <i1> [#uses=1]
br i1 %tmp2942, label %bb31, label %bb26
bb26: ; preds = %bb26, %entry
; CHECK: movq ({{.*}},8), %mm
; CHECK: paddq ({{.*}},8), %mm
; CHECK: paddq %mm{{[0-7]}}, %mm
%i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3]
%sum.035.0 = phi x86_mmx [ %tmp2943, %entry ], [ %tmp22, %bb26 ] ; <x86_mmx> [#uses=1]
%tmp13 = getelementptr x86_mmx* %b, i32 %i.037.0 ; <x86_mmx*> [#uses=1]
%tmp14 = load x86_mmx* %tmp13 ; <x86_mmx> [#uses=1]
%tmp18 = getelementptr x86_mmx* %a, i32 %i.037.0 ; <x86_mmx*> [#uses=1]
%tmp19 = load x86_mmx* %tmp18 ; <x86_mmx> [#uses=1]
%tmp21 = call x86_mmx @llvm.x86.mmx.padd.q (x86_mmx %tmp19, x86_mmx %tmp14) ; <x86_mmx> [#uses=1]
%tmp22 = call x86_mmx @llvm.x86.mmx.padd.q (x86_mmx %tmp21, x86_mmx %sum.035.0) ; <x86_mmx> [#uses=2]
%tmp25 = add i32 %i.037.0, 1 ; <i32> [#uses=2]
%tmp29 = icmp ult i32 %tmp25, %count ; <i1> [#uses=1]
br i1 %tmp29, label %bb26, label %bb31
bb31: ; preds = %bb26, %entry
%sum.035.1 = phi x86_mmx [ %tmp2943, %entry ], [ %tmp22, %bb26 ] ; <x86_mmx> [#uses=1]
%t = bitcast x86_mmx %sum.035.1 to <1 x i64>
ret <1 x i64> %t
}
declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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