2016-11-13 08:01:11 +01:00
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure fdiv is promoted to f32.
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; GCN-LABEL: {{^}}fdiv_f16
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2016-12-22 04:05:41 +01:00
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; SI: v_cvt_f32_f16
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; SI: v_cvt_f32_f16
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; SI: v_div_scale_f32
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; SI-DAG: v_div_scale_f32
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; SI-DAG: v_rcp_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_mul_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_fma_f32
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; SI: v_div_fmas_f32
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; SI: v_div_fixup_f32
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; SI: v_cvt_f16_f32
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; VI: buffer_load_ushort [[LHS:v[0-9]+]]
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; VI: buffer_load_ushort [[RHS:v[0-9]+]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_LHS:v[0-9]+]], [[LHS]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_RHS:v[0-9]+]], [[RHS]]
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; VI-DAG: v_rcp_f32_e32 [[RCP_RHS:v[0-9]+]], [[CVT_RHS]]
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; VI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[RCP_RHS]], [[CVT_LHS]]
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; VI: v_cvt_f16_f32_e32 [[CVT_BACK:v[0-9]+]], [[MUL]]
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; VI: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
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; VI: buffer_store_short [[RESULT]]
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2016-11-13 08:01:11 +01:00
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define void @fdiv_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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entry:
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2016-12-22 04:05:41 +01:00
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%a.val = load volatile half, half addrspace(1)* %a
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%b.val = load volatile half, half addrspace(1)* %b
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2016-11-13 08:01:11 +01:00
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%r.val = fdiv half %a.val, %b.val
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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