2017-11-13 00:53:44 +01:00
|
|
|
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
|
|
|
|
|
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
|
2016-05-05 22:07:37 +02:00
|
|
|
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
|
2012-12-11 22:25:42 +01:00
|
|
|
|
2015-09-25 20:21:47 +02:00
|
|
|
declare i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}test2:
|
2014-06-09 10:36:53 +02:00
|
|
|
; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
2012-12-11 22:25:42 +01:00
|
|
|
|
2017-07-04 19:32:00 +02:00
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
2013-06-25 15:55:23 +02:00
|
|
|
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-27 20:29:02 +01:00
|
|
|
%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
|
2015-02-27 22:17:42 +01:00
|
|
|
%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
|
|
|
|
|
%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
|
2013-06-25 15:55:23 +02:00
|
|
|
%result = and <2 x i32> %a, %b
|
|
|
|
|
store <2 x i32> %result, <2 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}test4:
|
2014-06-09 10:36:53 +02:00
|
|
|
; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
|
|
|
|
; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
|
2013-06-25 15:55:23 +02:00
|
|
|
|
2017-07-04 19:32:00 +02:00
|
|
|
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
|
2013-06-25 15:55:23 +02:00
|
|
|
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
|
[opaque pointer type] Add textual IR support for explicit type parameter to getelementptr instruction
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
2015-02-27 20:29:02 +01:00
|
|
|
%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
|
2015-02-27 22:17:42 +01:00
|
|
|
%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
|
|
|
|
|
%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
|
2012-12-11 22:25:42 +01:00
|
|
|
%result = and <4 x i32> %a, %b
|
|
|
|
|
store <4 x i32> %result, <4 x i32> addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-06-09 10:36:53 +02:00
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}s_and_i32:
|
2014-11-05 15:50:53 +01:00
|
|
|
; SI: s_and_b32
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i32 %a, %b
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}s_and_constant_i32:
|
2014-11-05 15:50:53 +01:00
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i32 %a, 1234567
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-25 20:21:47 +02:00
|
|
|
; FIXME: We should really duplicate the constant so that the SALU use
|
|
|
|
|
; can fold into the s_and_b32 and the VALU one is materialized
|
|
|
|
|
; directly without copying from the SGPR.
|
|
|
|
|
|
|
|
|
|
; Second use is a VGPR use of the constant.
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_0:
|
|
|
|
|
; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687
|
|
|
|
|
; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
|
|
|
|
|
; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]]
|
|
|
|
|
; SI: buffer_store_dword [[VK]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_multi_use_constant_i32_0(i32 addrspace(1)* %out, i32 %a, i32 %b) {
|
2015-09-25 20:21:47 +02:00
|
|
|
%and = and i32 %a, 1234567
|
|
|
|
|
|
|
|
|
|
; Just to stop future replacement of copy to vgpr + store with VALU op.
|
|
|
|
|
%foo = add i32 %and, %b
|
|
|
|
|
store volatile i32 %foo, i32 addrspace(1)* %out
|
|
|
|
|
store volatile i32 1234567, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Second use is another SGPR use of the constant.
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_1:
|
|
|
|
|
; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687
|
|
|
|
|
; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
|
|
|
|
|
; SI: s_add_i32
|
|
|
|
|
; SI: s_add_i32 [[ADD:s[0-9]+]], s{{[0-9]+}}, [[K]]
|
2017-11-13 00:53:44 +01:00
|
|
|
; SI: v_mov_b32_e32 [[VADD:v[0-9]+]], [[ADD]]
|
|
|
|
|
; SI: buffer_store_dword [[VADD]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_multi_use_constant_i32_1(i32 addrspace(1)* %out, i32 %a, i32 %b) {
|
2015-09-25 20:21:47 +02:00
|
|
|
%and = and i32 %a, 1234567
|
|
|
|
|
%foo = add i32 %and, 1234567
|
|
|
|
|
%bar = add i32 %foo, %b
|
|
|
|
|
store volatile i32 %bar, i32 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_i32_vgpr_vgpr:
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
|
2015-09-25 20:21:47 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i32, i32 addrspace(1)* %gep.a
|
|
|
|
|
%b = load i32, i32 addrspace(1)* %gep.b
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i32 %a, %b
|
2015-09-25 20:21:47 +02:00
|
|
|
store i32 %and, i32 addrspace(1)* %gep.out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_i32_sgpr_vgpr:
|
|
|
|
|
; SI-DAG: s_load_dword [[SA:s[0-9]+]]
|
|
|
|
|
; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i32 addrspace(1)* %bptr) {
|
2015-09-25 20:21:47 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%b = load i32, i32 addrspace(1)* %gep.b
|
|
|
|
|
%and = and i32 %a, %b
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %gep.out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_i32_vgpr_sgpr:
|
|
|
|
|
; SI-DAG: s_load_dword [[SA:s[0-9]+]]
|
|
|
|
|
; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 %b) {
|
2015-09-25 20:21:47 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
|
|
|
|
|
%a = load i32, i32 addrspace(1)* %gep.a
|
|
|
|
|
%and = and i32 %a, %b
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %gep.out
|
2014-06-09 10:36:53 +02:00
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-13 20:05:03 +01:00
|
|
|
; FUNC-LABEL: {{^}}v_and_constant_i32
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i32, i32 addrspace(1)* %gep, align 4
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i32 %a, 1234567
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-13 20:05:03 +01:00
|
|
|
; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i32, i32 addrspace(1)* %gep, align 4
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i32 %a, 64
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
|
|
|
|
|
; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i32, i32 addrspace(1)* %gep, align 4
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i32 %a, -16
|
|
|
|
|
store i32 %and, i32 addrspace(1)* %out, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_i64
|
2014-11-05 15:50:53 +01:00
|
|
|
; SI: s_and_b64
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i64 %a, %b
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}s_and_i1:
|
AMDGPU: Try a lot harder to emit scalar loads
This has two main components. First, widen
widen short constant loads in DAG when they have
the correct alignment. This is already done a bit in
AMDGPUCodeGenPrepare, since that has access to
DivergenceAnalysis. This can't help kernarg loads
created in the DAG. Start to use DAG divergence analysis
to help this case.
The second part is to avoid kernel argument lowering
breaking the alignment of short vector elements because
calling convention lowering wants to split everything
into legal register types.
When loading a split type, load the nearest 4-byte aligned
segment and shift to get the desired bits. This extra
load of the earlier argument piece ends up merging,
and the bit extract hopefully folds out.
There are a number of improvements and regressions with
this, but I think as-is this is a better compromise between
several of the worst parts of SelectionDAG.
Particularly when i16 is legal, this produces worse code
for i8 and i16 element vector kernel arguments. This is
partially due to the very weak load merging the DAG does.
It only looks for fairly specific combines between pairs
of loads which no longer appear. In particular this
causes v4i16 loads to be split into 2 components when
previously the two halves were merged.
Worse, because of the newly introduced shifts, there
is a lot more unnecessary vector packing and unpacking code
emitted. At least some of this is due to reporting
false for isTypeDesirableForOp for i16 as a workaround for
the lack of divergence information in the DAG. The cases
where this happens it doesn't actually matter, but the
relevant code in SimplifyDemandedBits doens't have the context
to know to ignore this.
The use of the scalar cache is probably more important
than the mess of mostly scalar instructions doing this packing
and unpacking. Future work can fix this, possibly by making better
use of the new DAG divergence information for controlling promotion
decisions, or adding another version of shift + trunc + shift
combines that doesn't only know about the used types.
llvm-svn: 334180
2018-06-07 11:54:49 +02:00
|
|
|
; SI: s_load_dword [[LOAD:s[0-9]+]]
|
|
|
|
|
; SI: s_lshr_b32 [[B_SHIFT:s[0-9]+]], [[LOAD]], 8
|
|
|
|
|
; SI: s_and_b32 [[AND:s[0-9]+]], [[LOAD]], [[B_SHIFT]]
|
|
|
|
|
; SI: s_and_b32 [[AND_TRUNC:s[0-9]+]], [[AND]], 1{{$}}
|
|
|
|
|
; SI: v_mov_b32_e32 [[V_AND_TRUNC:v[0-9]+]], [[AND_TRUNC]]
|
|
|
|
|
; SI: buffer_store_byte [[V_AND_TRUNC]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
|
2014-07-15 23:44:37 +02:00
|
|
|
%and = and i1 %a, %b
|
|
|
|
|
store i1 %and, i1 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_constant_i64:
|
|
|
|
|
; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}}
|
|
|
|
|
; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}}
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%and = and i64 %a, 549756338176
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64:
|
|
|
|
|
; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}}
|
|
|
|
|
; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}}
|
|
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%and0 = and i64 %a, 549756338176
|
|
|
|
|
%and1 = and i64 %b, 549756338176
|
|
|
|
|
store volatile i64 %and0, i64 addrspace(1)* %out
|
|
|
|
|
store volatile i64 %and1, i64 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64:
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}}
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-26 21:10:00 +02:00
|
|
|
define amdgpu_kernel void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i32, i64 %a) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%and = and i64 %a, 1234567
|
2014-06-09 10:36:53 +02:00
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64:
|
2017-09-19 22:54:38 +02:00
|
|
|
; SI: s_load_dwordx2
|
2016-04-23 00:48:38 +02:00
|
|
|
; SI: s_load_dword [[A:s[0-9]+]]
|
|
|
|
|
; SI: s_load_dword [[B:s[0-9]+]]
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
2016-04-23 00:48:38 +02:00
|
|
|
; SI: s_lshl_b32 [[A]], [[A]], 1
|
|
|
|
|
; SI: s_lshl_b32 [[B]], [[B]], 1
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, [[A]], 62
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, [[B]], 62
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-26 21:10:00 +02:00
|
|
|
define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i32, i64 %a, i32, i64 %b, i32, i64 %c) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%shl.a = shl i64 %a, 1
|
|
|
|
|
%shl.b = shl i64 %b, 1
|
|
|
|
|
%and0 = and i64 %shl.a, 62
|
|
|
|
|
%and1 = and i64 %shl.b, 62
|
|
|
|
|
%add0 = add i64 %and0, %c
|
|
|
|
|
%add1 = add i64 %and1, %c
|
|
|
|
|
store volatile i64 %add0, i64 addrspace(1)* %out
|
|
|
|
|
store volatile i64 %add1, i64 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}v_and_i64:
|
2014-11-05 15:50:53 +01:00
|
|
|
; SI: v_and_b32
|
|
|
|
|
; SI: v_and_b32
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
|
|
|
|
%gep.b = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
|
|
|
|
|
%b = load i64, i64 addrspace(1)* %gep.b, align 8
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i64 %a, %b
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}v_and_constant_i64:
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}}
|
|
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}}
|
2015-09-24 10:36:14 +02:00
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
2015-09-24 10:36:14 +02:00
|
|
|
%and = and i64 %a, 1231231234567
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64:
|
2016-08-29 21:42:52 +02:00
|
|
|
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
|
|
|
|
|
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
|
2016-08-29 21:42:52 +02:00
|
|
|
; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}}
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
|
|
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
|
|
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]]
|
|
|
|
|
; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]]
|
|
|
|
|
; SI: buffer_store_dwordx2
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%a = load volatile i64, i64 addrspace(1)* %aptr
|
|
|
|
|
%b = load volatile i64, i64 addrspace(1)* %aptr
|
|
|
|
|
%and0 = and i64 %a, 1231231234567
|
|
|
|
|
%and1 = and i64 %b, 1231231234567
|
|
|
|
|
store volatile i64 %and0, i64 addrspace(1)* %out
|
|
|
|
|
store volatile i64 %and1, i64 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64:
|
|
|
|
|
; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]]
|
2016-03-30 18:35:09 +02:00
|
|
|
; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]]
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
2016-08-29 21:42:52 +02:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]]
|
2016-03-30 18:35:09 +02:00
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]]
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%a = load volatile i64, i64 addrspace(1)* %aptr
|
|
|
|
|
%b = load volatile i64, i64 addrspace(1)* %aptr
|
|
|
|
|
%and0 = and i64 %a, 63
|
|
|
|
|
%and1 = and i64 %b, 63
|
|
|
|
|
store volatile i64 %and0, i64 addrspace(1)* %out
|
|
|
|
|
store volatile i64 %and1, i64 addrspace(1)* %out
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-24 10:36:14 +02:00
|
|
|
; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant:
|
2017-07-04 19:32:00 +02:00
|
|
|
; SI: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]]
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
2014-06-09 10:36:53 +02:00
|
|
|
%and = and i64 %a, 1234567
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2014-09-15 19:15:02 +02:00
|
|
|
|
2014-10-01 19:15:17 +02:00
|
|
|
; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
|
2017-07-04 19:32:00 +02:00
|
|
|
; SI: {{buffer|flat}}_load_dword v{{[0-9]+}}
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
2014-11-05 15:50:53 +01:00
|
|
|
; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
2014-09-15 19:15:02 +02:00
|
|
|
%and = and i64 %a, 64
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-09-14 17:19:03 +02:00
|
|
|
; FIXME: Should be able to reduce load width
|
|
|
|
|
; FUNC-LABEL: {{^}}v_and_inline_neg_imm_i64:
|
2017-07-04 19:32:00 +02:00
|
|
|
; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
2016-09-14 17:19:03 +02:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: v_and_b32_e32 v[[VAL_LO]], -8, v[[VAL_LO]]
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
2017-07-04 19:32:00 +02:00
|
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
|
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
|
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
2016-09-14 17:19:03 +02:00
|
|
|
%and = and i64 %a, -8
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-13 20:05:03 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI: s_load_dword
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dword
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2014-09-15 19:15:02 +02:00
|
|
|
%and = and i64 %a, 64
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
2015-02-13 20:05:03 +01:00
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink:
|
2016-04-23 00:48:38 +02:00
|
|
|
; SI: s_load_dword [[A:s[0-9]+]]
|
|
|
|
|
; SI: s_lshl_b32 [[A]], [[A]], 1{{$}}
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
2016-04-23 00:48:38 +02:00
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, [[A]], 64
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_add_u32
|
|
|
|
|
; SI-NEXT: s_addc_u32
|
AMDGPU: Add pass to lower kernel arguments to loads
This replaces most argument uses with loads, but for
now not all.
The code in SelectionDAG for calling convention lowering
is actively harmful for amdgpu_kernel. It attempts to
split the argument types into register legal types, which
results in low quality code for arbitary types. Since
all kernel arguments are passed in memory, we just want the
raw types.
I've tried a couple of methods of mitigating this in SelectionDAG,
but it's easier to just bypass this problem alltogether. It's
possible to hack around the problem in the initial lowering,
but the real problem is the DAG then expects to be able to use
CopyToReg/CopyFromReg for uses of the arguments outside the block.
Exposing the argument loads in the IR also has the advantage
that the LoadStoreVectorizer can merge them.
I'm not sure the best approach to dealing with the IR
argument list is. The patch as-is just leaves the IR arguments
in place, so all the existing code will still compute the same
kernarg size and pointlessly lowers the arguments.
Arguably the frontend should emit kernels with an empty argument
list in the first place. Alternatively a dummy array could be
inserted as a single argument just to reserve space.
This does have some disadvantages. Local pointer kernel arguments can
no longer have AssertZext placed on them as the equivalent !range
metadata is not valid on pointer typed loads. This is mostly bad
for SI which needs to know about the known bits in order to use the
DS instruction offset, so in this case this is not done.
More importantly, this skips noalias arguments since this pass
does not yet convert this to the equivalent !alias.scope and !noalias
metadata. Producing this metadata correctly seems to be tricky,
although this logically is the same as inlining into a function which
doesn't exist. Additionally, exposing these loads to the vectorizer
may result in degraded aliasing information if a pointer load is
merged with another argument load.
I'm also not entirely sure this is preserving the current clover
ABI, although I would greatly prefer if it would stop widening
arguments and match the HSA ABI. As-is I think it is extending
< 4-byte arguments to 4-bytes but doesn't align them to 4-bytes.
llvm-svn: 335650
2018-06-26 21:10:00 +02:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i32, i64 %b) {
|
2016-01-18 23:01:13 +01:00
|
|
|
%shl = shl i64 %a, 1
|
|
|
|
|
%and = and i64 %shl, 64
|
|
|
|
|
%add = add i64 %and, %b
|
|
|
|
|
store i64 %add, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-02-13 20:05:03 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 1
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
|
2016-01-18 23:01:13 +01:00
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 4607182418800017408
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
|
2016-01-18 23:01:13 +01:00
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 13830554455654793216
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
|
2016-01-18 23:01:13 +01:00
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 4602678819172646912
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64:
|
|
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 13826050856027422720
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64:
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 4611686018427387904
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64:
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 13835058055282163712
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64:
|
|
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 4616189618054758400
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64:
|
|
|
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
|
|
|
|
|
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI: s_load_dwordx2
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000
|
|
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 13839561654909534208
|
|
|
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; Test with the 64-bit integer bitpattern for a 32-bit float in the
|
|
|
|
|
; low 32-bits, which is not a valid 64-bit inline immmediate.
|
|
|
|
|
|
2016-01-18 23:01:13 +01:00
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64:
|
2016-06-25 02:23:00 +02:00
|
|
|
; SI: s_load_dwordx2
|
2016-08-29 21:42:52 +02:00
|
|
|
; SI: s_load_dword s
|
2016-01-18 23:01:13 +01:00
|
|
|
; SI-NOT: and
|
|
|
|
|
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
|
|
|
|
|
; SI-NOT: and
|
|
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; SI: buffer_store_dwordx2
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2017-03-21 22:39:51 +01:00
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define amdgpu_kernel void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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2015-02-13 20:05:03 +01:00
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%and = and i64 %a, 1082130432
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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2016-01-18 23:01:13 +01:00
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; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64:
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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2017-03-21 22:39:51 +01:00
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define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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2015-02-13 20:05:03 +01:00
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%and = and i64 %a, -1065353216
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; Shift into upper 32-bits
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2016-01-18 23:01:13 +01:00
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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2017-03-21 22:39:51 +01:00
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define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
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2015-02-13 20:05:03 +01:00
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%and = and i64 %a, 4647714815446351872
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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|
2016-01-18 23:01:13 +01:00
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; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64:
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; SI: s_load_dwordx2
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
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; SI-NOT: and
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; SI: buffer_store_dwordx2
|
2017-03-21 22:39:51 +01:00
|
|
|
define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
2015-02-13 20:05:03 +01:00
|
|
|
%and = and i64 %a, 13871086852301127680
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
|
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}
|
2015-09-25 20:21:47 +02:00
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attributes #0 = { nounwind readnone }
|
