2018-11-28 12:38:10 +01:00
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//===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
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//
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2019-01-19 09:50:56 +01:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-11-28 12:38:10 +01:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise ARM hardware features
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// such as FPU/CPU/ARCH/extensions and specific support such as HWDIV.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMTargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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2018-11-28 16:12:33 +01:00
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#include <cctype>
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2018-11-28 12:38:10 +01:00
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using namespace llvm;
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static StringRef getHWDivSynonym(StringRef HWDiv) {
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return StringSwitch<StringRef>(HWDiv)
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.Case("thumb,arm", "arm,thumb")
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.Default(HWDiv);
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}
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// Allows partial match, ex. "v7a" matches "armv7a".
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ARM::ArchKind ARM::parseArch(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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StringRef Syn = getArchSynonym(Arch);
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for (const auto A : ARCHNames) {
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if (A.getName().endswith(Syn))
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return A.ID;
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}
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return ArchKind::INVALID;
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}
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// Version number (ex. v7 = 7).
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unsigned ARM::parseArchVersion(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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switch (parseArch(Arch)) {
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case ArchKind::ARMV2:
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case ArchKind::ARMV2A:
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return 2;
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case ArchKind::ARMV3:
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case ArchKind::ARMV3M:
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return 3;
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case ArchKind::ARMV4:
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case ArchKind::ARMV4T:
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return 4;
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case ArchKind::ARMV5T:
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case ArchKind::ARMV5TE:
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case ArchKind::IWMMXT:
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case ArchKind::IWMMXT2:
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case ArchKind::XSCALE:
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case ArchKind::ARMV5TEJ:
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return 5;
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case ArchKind::ARMV6:
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case ArchKind::ARMV6K:
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case ArchKind::ARMV6T2:
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case ArchKind::ARMV6KZ:
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case ArchKind::ARMV6M:
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return 6;
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case ArchKind::ARMV7A:
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case ArchKind::ARMV7VE:
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case ArchKind::ARMV7R:
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case ArchKind::ARMV7M:
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case ArchKind::ARMV7S:
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case ArchKind::ARMV7EM:
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case ArchKind::ARMV7K:
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return 7;
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case ArchKind::ARMV8A:
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case ArchKind::ARMV8_1A:
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case ArchKind::ARMV8_2A:
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case ArchKind::ARMV8_3A:
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case ArchKind::ARMV8_4A:
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case ArchKind::ARMV8_5A:
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case ArchKind::ARMV8R:
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case ArchKind::ARMV8MBaseline:
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case ArchKind::ARMV8MMainline:
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2019-05-30 14:57:04 +02:00
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case ArchKind::ARMV8_1MMainline:
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2018-11-28 12:38:10 +01:00
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return 8;
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case ArchKind::INVALID:
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return 0;
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}
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llvm_unreachable("Unhandled architecture");
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}
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// Profile A/R/M
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ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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switch (parseArch(Arch)) {
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case ArchKind::ARMV6M:
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case ArchKind::ARMV7M:
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case ArchKind::ARMV7EM:
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case ArchKind::ARMV8MMainline:
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case ArchKind::ARMV8MBaseline:
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2019-05-30 14:57:04 +02:00
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case ArchKind::ARMV8_1MMainline:
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2018-11-28 12:38:10 +01:00
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return ProfileKind::M;
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case ArchKind::ARMV7R:
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case ArchKind::ARMV8R:
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return ProfileKind::R;
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case ArchKind::ARMV7A:
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case ArchKind::ARMV7VE:
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case ArchKind::ARMV7K:
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case ArchKind::ARMV8A:
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case ArchKind::ARMV8_1A:
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case ArchKind::ARMV8_2A:
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case ArchKind::ARMV8_3A:
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case ArchKind::ARMV8_4A:
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case ArchKind::ARMV8_5A:
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return ProfileKind::A;
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case ArchKind::ARMV2:
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case ArchKind::ARMV2A:
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case ArchKind::ARMV3:
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case ArchKind::ARMV3M:
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case ArchKind::ARMV4:
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case ArchKind::ARMV4T:
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case ArchKind::ARMV5T:
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case ArchKind::ARMV5TE:
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case ArchKind::ARMV5TEJ:
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case ArchKind::ARMV6:
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case ArchKind::ARMV6K:
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case ArchKind::ARMV6T2:
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case ArchKind::ARMV6KZ:
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case ArchKind::ARMV7S:
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case ArchKind::IWMMXT:
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case ArchKind::IWMMXT2:
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case ArchKind::XSCALE:
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case ArchKind::INVALID:
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return ProfileKind::INVALID;
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}
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llvm_unreachable("Unhandled architecture");
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}
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StringRef ARM::getArchSynonym(StringRef Arch) {
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return StringSwitch<StringRef>(Arch)
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.Case("v5", "v5t")
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.Case("v5e", "v5te")
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.Case("v6j", "v6")
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.Case("v6hl", "v6k")
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.Cases("v6m", "v6sm", "v6s-m", "v6-m")
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.Cases("v6z", "v6zk", "v6kz")
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.Cases("v7", "v7a", "v7hl", "v7l", "v7-a")
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.Case("v7r", "v7-r")
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.Case("v7m", "v7-m")
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.Case("v7em", "v7e-m")
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.Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a")
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.Case("v8.1a", "v8.1-a")
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.Case("v8.2a", "v8.2-a")
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.Case("v8.3a", "v8.3-a")
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.Case("v8.4a", "v8.4-a")
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.Case("v8.5a", "v8.5-a")
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.Case("v8r", "v8-r")
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.Case("v8m.base", "v8-m.base")
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.Case("v8m.main", "v8-m.main")
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2019-05-30 14:57:04 +02:00
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.Case("v8.1m.main", "v8.1-m.main")
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2018-11-28 12:38:10 +01:00
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.Default(Arch);
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}
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bool ARM::getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features) {
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if (FPUKind >= FK_LAST || FPUKind == FK_INVALID)
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return false;
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// FPU version subtarget features are inclusive of lower-numbered ones, so
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// enable the one corresponding to this version and disable all that are
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// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
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// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
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switch (FPUNames[FPUKind].FPUVer) {
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2019-05-30 14:57:04 +02:00
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case FPUVersion::VFPV5_FULLFP16:
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Features.push_back("+fp-armv8");
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Features.push_back("+fullfp16");
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break;
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2018-11-28 12:38:10 +01:00
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case FPUVersion::VFPV5:
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Features.push_back("+fp-armv8");
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break;
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case FPUVersion::VFPV4:
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Features.push_back("+vfp4");
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Features.push_back("-fp-armv8");
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break;
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case FPUVersion::VFPV3_FP16:
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Features.push_back("+vfp3");
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Features.push_back("+fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case FPUVersion::VFPV3:
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Features.push_back("+vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case FPUVersion::VFPV2:
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Features.push_back("+vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case FPUVersion::NONE:
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[ARM] Fix recent breakage of -mfpu=none.
The recent change D60691 introduced a bug in clang when handling
option combinations such as `-mcpu=cortex-m4 -mfpu=none`. Those
options together should select Cortex-M4 but disable all use of
hardware FP, but in fact, now hardware FP instructions can still be
generated in that mode.
The reason is because the handling of FPUVersion::NONE disables all
the same feature names it used to, of which the base one is `vfp2`.
But now there are further features below that, like `vfp2d16fp` and
(following D60694) `fpregs`, which also need to be turned off to
disable hardware FP completely.
Added a tiny test which double-checks that compiling a simple FP
function doesn't access the FP registers.
Reviewers: SjoerdMeijer, dmgreen
Reviewed By: dmgreen
Subscribers: lebedev.ri, javed.absar, kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D62729
llvm-svn: 362380
2019-06-03 13:02:53 +02:00
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Features.push_back("-fpregs");
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2018-11-28 12:38:10 +01:00
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Features.push_back("-vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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}
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[ARM] Replace fp-only-sp and d16 with fp64 and d32.
Those two subtarget features were awkward because their semantics are
reversed: each one indicates the _lack_ of support for something in
the architecture, rather than the presence. As a consequence, you
don't get the behavior you want if you combine two sets of feature
bits.
Each SubtargetFeature for an FP architecture version now comes in four
versions, one for each combination of those options. So you can still
say (for example) '+vfp2' in a feature string and it will mean what
it's always meant, but there's a new string '+vfp2d16sp' meaning the
version without those extra options.
A lot of this change is just mechanically replacing positive checks
for the old features with negative checks for the new ones. But one
more interesting change is that I've rearranged getFPUFeatures() so
that the main FPU feature is appended to the output list *before*
rather than after the features derived from the Restriction field, so
that -fp64 and -d32 can override defaults added by the main feature.
Reviewers: dmgreen, samparker, SjoerdMeijer
Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D60691
llvm-svn: 361845
2019-05-28 18:13:20 +02:00
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// fp64 and d32 subtarget features are independent of each other, so we
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// must disable/enable both.
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if (FPUKind == FK_NONE) {
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Features.push_back("-fp64");
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Features.push_back("-d32");
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} else {
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switch (FPUNames[FPUKind].Restriction) {
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case FPURestriction::SP_D16:
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Features.push_back("-fp64");
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Features.push_back("-d32");
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break;
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case FPURestriction::D16:
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Features.push_back("+fp64");
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Features.push_back("-d32");
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break;
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case FPURestriction::None:
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Features.push_back("+fp64");
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Features.push_back("+d32");
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break;
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}
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}
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2018-11-28 12:38:10 +01:00
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// crypto includes neon, so we handle this similarly to FPU version.
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switch (FPUNames[FPUKind].NeonSupport) {
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case NeonSupportLevel::Crypto:
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Features.push_back("+neon");
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Features.push_back("+crypto");
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break;
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case NeonSupportLevel::Neon:
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Features.push_back("+neon");
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Features.push_back("-crypto");
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break;
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case NeonSupportLevel::None:
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Features.push_back("-neon");
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Features.push_back("-crypto");
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break;
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}
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return true;
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}
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// Little/Big endian
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ARM::EndianKind ARM::parseArchEndian(StringRef Arch) {
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if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
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Arch.startswith("aarch64_be"))
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return EndianKind::BIG;
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if (Arch.startswith("arm") || Arch.startswith("thumb")) {
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if (Arch.endswith("eb"))
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return EndianKind::BIG;
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else
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return EndianKind::LITTLE;
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}
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2019-05-14 13:25:44 +02:00
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if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32"))
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2018-11-28 12:38:10 +01:00
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return EndianKind::LITTLE;
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return EndianKind::INVALID;
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}
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// ARM, Thumb, AArch64
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ARM::ISAKind ARM::parseArchISA(StringRef Arch) {
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return StringSwitch<ISAKind>(Arch)
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.StartsWith("aarch64", ISAKind::AARCH64)
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.StartsWith("arm64", ISAKind::AARCH64)
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.StartsWith("thumb", ISAKind::THUMB)
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.StartsWith("arm", ISAKind::ARM)
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.Default(ISAKind::INVALID);
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}
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unsigned ARM::parseFPU(StringRef FPU) {
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StringRef Syn = getFPUSynonym(FPU);
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for (const auto F : FPUNames) {
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if (Syn == F.getName())
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return F.ID;
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}
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return FK_INVALID;
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}
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ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= FK_LAST)
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return NeonSupportLevel::None;
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return FPUNames[FPUKind].NeonSupport;
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}
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// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
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// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
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// "v.+", if the latter, return unmodified string, minus 'eb'.
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// If invalid, return empty string.
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StringRef ARM::getCanonicalArchName(StringRef Arch) {
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size_t offset = StringRef::npos;
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StringRef A = Arch;
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StringRef Error = "";
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// Begins with "arm" / "thumb", move past it.
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2019-05-14 13:25:44 +02:00
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if (A.startswith("arm64_32"))
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offset = 8;
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else if (A.startswith("arm64"))
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2018-11-28 12:38:10 +01:00
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offset = 5;
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2019-05-14 13:25:44 +02:00
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else if (A.startswith("aarch64_32"))
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offset = 10;
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2018-11-28 12:38:10 +01:00
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|
|
else if (A.startswith("arm"))
|
|
|
|
offset = 3;
|
|
|
|
else if (A.startswith("thumb"))
|
|
|
|
offset = 5;
|
|
|
|
else if (A.startswith("aarch64")) {
|
|
|
|
offset = 7;
|
|
|
|
// AArch64 uses "_be", not "eb" suffix.
|
|
|
|
if (A.find("eb") != StringRef::npos)
|
|
|
|
return Error;
|
|
|
|
if (A.substr(offset, 3) == "_be")
|
|
|
|
offset += 3;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Ex. "armebv7", move past the "eb".
|
|
|
|
if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
|
|
|
|
offset += 2;
|
|
|
|
// Or, if it ends with eb ("armv7eb"), chop it off.
|
|
|
|
else if (A.endswith("eb"))
|
|
|
|
A = A.substr(0, A.size() - 2);
|
|
|
|
// Trim the head
|
|
|
|
if (offset != StringRef::npos)
|
|
|
|
A = A.substr(offset);
|
|
|
|
|
|
|
|
// Empty string means offset reached the end, which means it's valid.
|
|
|
|
if (A.empty())
|
|
|
|
return Arch;
|
|
|
|
|
|
|
|
// Only match non-marketing names
|
|
|
|
if (offset != StringRef::npos) {
|
|
|
|
// Must start with 'vN'.
|
|
|
|
if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1])))
|
|
|
|
return Error;
|
|
|
|
// Can't have an extra 'eb'.
|
|
|
|
if (A.find("eb") != StringRef::npos)
|
|
|
|
return Error;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Arch will either be a 'v' name (v7a) or a marketing name (xscale).
|
|
|
|
return A;
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getFPUSynonym(StringRef FPU) {
|
|
|
|
return StringSwitch<StringRef>(FPU)
|
|
|
|
.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
|
|
|
|
.Case("vfp2", "vfpv2")
|
|
|
|
.Case("vfp3", "vfpv3")
|
|
|
|
.Case("vfp4", "vfpv4")
|
|
|
|
.Case("vfp3-d16", "vfpv3-d16")
|
|
|
|
.Case("vfp4-d16", "vfpv4-d16")
|
|
|
|
.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
|
|
|
|
.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
|
|
|
|
.Case("fp5-sp-d16", "fpv5-sp-d16")
|
|
|
|
.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
|
|
|
|
// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
|
|
|
|
.Case("neon-vfpv3", "neon")
|
|
|
|
.Default(FPU);
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getFPUName(unsigned FPUKind) {
|
|
|
|
if (FPUKind >= FK_LAST)
|
|
|
|
return StringRef();
|
|
|
|
return FPUNames[FPUKind].getName();
|
|
|
|
}
|
|
|
|
|
|
|
|
ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) {
|
|
|
|
if (FPUKind >= FK_LAST)
|
|
|
|
return FPUVersion::NONE;
|
|
|
|
return FPUNames[FPUKind].FPUVer;
|
|
|
|
}
|
|
|
|
|
|
|
|
ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) {
|
|
|
|
if (FPUKind >= FK_LAST)
|
|
|
|
return FPURestriction::None;
|
|
|
|
return FPUNames[FPUKind].Restriction;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) {
|
|
|
|
if (CPU == "generic")
|
|
|
|
return ARM::ARCHNames[static_cast<unsigned>(AK)].DefaultFPU;
|
|
|
|
|
|
|
|
return StringSwitch<unsigned>(CPU)
|
|
|
|
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
|
|
|
|
.Case(NAME, DEFAULT_FPU)
|
|
|
|
#include "llvm/Support/ARMTargetParser.def"
|
|
|
|
.Default(ARM::FK_INVALID);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) {
|
|
|
|
if (CPU == "generic")
|
|
|
|
return ARM::ARCHNames[static_cast<unsigned>(AK)].ArchBaseExtensions;
|
|
|
|
|
|
|
|
return StringSwitch<unsigned>(CPU)
|
|
|
|
#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
|
|
|
|
.Case(NAME, \
|
|
|
|
ARCHNames[static_cast<unsigned>(ArchKind::ID)].ArchBaseExtensions | \
|
|
|
|
DEFAULT_EXT)
|
|
|
|
#include "llvm/Support/ARMTargetParser.def"
|
|
|
|
.Default(ARM::AEK_INVALID);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARM::getHWDivFeatures(unsigned HWDivKind,
|
|
|
|
std::vector<StringRef> &Features) {
|
|
|
|
|
|
|
|
if (HWDivKind == AEK_INVALID)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (HWDivKind & AEK_HWDIVARM)
|
|
|
|
Features.push_back("+hwdiv-arm");
|
|
|
|
else
|
|
|
|
Features.push_back("-hwdiv-arm");
|
|
|
|
|
|
|
|
if (HWDivKind & AEK_HWDIVTHUMB)
|
|
|
|
Features.push_back("+hwdiv");
|
|
|
|
else
|
|
|
|
Features.push_back("-hwdiv");
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool ARM::getExtensionFeatures(unsigned Extensions,
|
|
|
|
std::vector<StringRef> &Features) {
|
|
|
|
|
|
|
|
if (Extensions == AEK_INVALID)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (Extensions & AEK_CRC)
|
|
|
|
Features.push_back("+crc");
|
|
|
|
else
|
|
|
|
Features.push_back("-crc");
|
|
|
|
|
|
|
|
if (Extensions & AEK_DSP)
|
|
|
|
Features.push_back("+dsp");
|
|
|
|
else
|
|
|
|
Features.push_back("-dsp");
|
|
|
|
|
|
|
|
if (Extensions & AEK_FP16FML)
|
|
|
|
Features.push_back("+fp16fml");
|
|
|
|
else
|
|
|
|
Features.push_back("-fp16fml");
|
|
|
|
|
|
|
|
if (Extensions & AEK_RAS)
|
|
|
|
Features.push_back("+ras");
|
|
|
|
else
|
|
|
|
Features.push_back("-ras");
|
|
|
|
|
|
|
|
if (Extensions & AEK_DOTPROD)
|
|
|
|
Features.push_back("+dotprod");
|
|
|
|
else
|
|
|
|
Features.push_back("-dotprod");
|
|
|
|
|
|
|
|
return getHWDivFeatures(Extensions, Features);
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getArchName(ARM::ArchKind AK) {
|
|
|
|
return ARCHNames[static_cast<unsigned>(AK)].getName();
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getCPUAttr(ARM::ArchKind AK) {
|
|
|
|
return ARCHNames[static_cast<unsigned>(AK)].getCPUAttr();
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getSubArch(ARM::ArchKind AK) {
|
|
|
|
return ARCHNames[static_cast<unsigned>(AK)].getSubArch();
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARM::getArchAttr(ARM::ArchKind AK) {
|
|
|
|
return ARCHNames[static_cast<unsigned>(AK)].ArchAttr;
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getArchExtName(unsigned ArchExtKind) {
|
|
|
|
for (const auto AE : ARCHExtNames) {
|
|
|
|
if (ArchExtKind == AE.ID)
|
|
|
|
return AE.getName();
|
|
|
|
}
|
|
|
|
return StringRef();
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getArchExtFeature(StringRef ArchExt) {
|
|
|
|
if (ArchExt.startswith("no")) {
|
|
|
|
StringRef ArchExtBase(ArchExt.substr(2));
|
|
|
|
for (const auto AE : ARCHExtNames) {
|
|
|
|
if (AE.NegFeature && ArchExtBase == AE.getName())
|
|
|
|
return StringRef(AE.NegFeature);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
for (const auto AE : ARCHExtNames) {
|
|
|
|
if (AE.Feature && ArchExt == AE.getName())
|
|
|
|
return StringRef(AE.Feature);
|
|
|
|
}
|
|
|
|
|
|
|
|
return StringRef();
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getHWDivName(unsigned HWDivKind) {
|
|
|
|
for (const auto D : HWDivNames) {
|
|
|
|
if (HWDivKind == D.ID)
|
|
|
|
return D.getName();
|
|
|
|
}
|
|
|
|
return StringRef();
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::getDefaultCPU(StringRef Arch) {
|
|
|
|
ArchKind AK = parseArch(Arch);
|
|
|
|
if (AK == ArchKind::INVALID)
|
|
|
|
return StringRef();
|
|
|
|
|
|
|
|
// Look for multiple AKs to find the default for pair AK+Name.
|
|
|
|
for (const auto CPU : CPUNames) {
|
|
|
|
if (CPU.ArchID == AK && CPU.Default)
|
|
|
|
return CPU.getName();
|
|
|
|
}
|
|
|
|
|
|
|
|
// If we can't find a default then target the architecture instead
|
|
|
|
return "generic";
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARM::parseHWDiv(StringRef HWDiv) {
|
|
|
|
StringRef Syn = getHWDivSynonym(HWDiv);
|
|
|
|
for (const auto D : HWDivNames) {
|
|
|
|
if (Syn == D.getName())
|
|
|
|
return D.ID;
|
|
|
|
}
|
|
|
|
return AEK_INVALID;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned ARM::parseArchExt(StringRef ArchExt) {
|
|
|
|
for (const auto A : ARCHExtNames) {
|
|
|
|
if (ArchExt == A.getName())
|
|
|
|
return A.ID;
|
|
|
|
}
|
|
|
|
return AEK_INVALID;
|
|
|
|
}
|
|
|
|
|
|
|
|
ARM::ArchKind ARM::parseCPUArch(StringRef CPU) {
|
|
|
|
for (const auto C : CPUNames) {
|
|
|
|
if (CPU == C.getName())
|
|
|
|
return C.ArchID;
|
|
|
|
}
|
|
|
|
return ArchKind::INVALID;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ARM::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values) {
|
|
|
|
for (const CpuNames<ArchKind> &Arch : CPUNames) {
|
|
|
|
if (Arch.ArchID != ArchKind::INVALID)
|
|
|
|
Values.push_back(Arch.getName());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) {
|
|
|
|
StringRef ArchName =
|
|
|
|
CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU));
|
|
|
|
|
|
|
|
if (TT.isOSBinFormatMachO()) {
|
|
|
|
if (TT.getEnvironment() == Triple::EABI ||
|
|
|
|
TT.getOS() == Triple::UnknownOS ||
|
|
|
|
parseArchProfile(ArchName) == ProfileKind::M)
|
|
|
|
return "aapcs";
|
|
|
|
if (TT.isWatchABI())
|
|
|
|
return "aapcs16";
|
|
|
|
return "apcs-gnu";
|
|
|
|
} else if (TT.isOSWindows())
|
|
|
|
// FIXME: this is invalid for WindowsCE.
|
|
|
|
return "aapcs";
|
|
|
|
|
|
|
|
// Select the default based on the platform.
|
|
|
|
switch (TT.getEnvironment()) {
|
|
|
|
case Triple::Android:
|
|
|
|
case Triple::GNUEABI:
|
|
|
|
case Triple::GNUEABIHF:
|
|
|
|
case Triple::MuslEABI:
|
|
|
|
case Triple::MuslEABIHF:
|
|
|
|
return "aapcs-linux";
|
|
|
|
case Triple::EABIHF:
|
|
|
|
case Triple::EABI:
|
|
|
|
return "aapcs";
|
|
|
|
default:
|
|
|
|
if (TT.isOSNetBSD())
|
|
|
|
return "apcs-gnu";
|
|
|
|
if (TT.isOSOpenBSD())
|
|
|
|
return "aapcs-linux";
|
|
|
|
return "aapcs";
|
|
|
|
}
|
|
|
|
}
|