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llvm-mirror/test/CodeGen/Mips/fp-indexed-ls.ll

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[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1
; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2
; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6
; RUN: llc -march=mips64el -mcpu=mips4 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
; RUN: llc -march=mips64el -mcpu=mips64 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4
; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6
; Check that [ls][dwu]xc1 are not emitted for nacl.
; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%struct.S = type <{ [4 x float] }>
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
%struct.S2 = type <{ [4 x double] }>
%struct.S3 = type <{ i8, float }>
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
@s = external global [4 x %struct.S]
@gf = external global float
@gd = external global double
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
@s2 = external global [4 x %struct.S2]
@s3 = external global %struct.S3
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
define float @foo0(float* nocapture %b, i32 %o) nounwind readonly {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo0:
; MIPS32R1: sll $[[T1:[0-9]+]], $5, 2
; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS32R1: lwc1 $f0, 0($[[T3]])
; MIPS32R2: sll $[[T1:[0-9]+]], $5, 2
; MIPS32R2: lwxc1 $f0, $[[T1]]($4)
; MIPS32R6: sll $[[T1:[0-9]+]], $5, 2
; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS32R6: lwc1 $f0, 0($[[T3]])
; MIPS4: sll $[[T0:[0-9]+]], $5, 0
; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 2
; MIPS4: lwxc1 $f0, $[[T1]]($4)
; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 2
; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS64R6: lwc1 $f0, 0($[[T3]])
[mips] Add NaCl target and forbid indexed loads and stores for it This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 llvm-svn: 200855
2014-02-05 18:19:30 +01:00
; CHECK-NACL-NOT: lwxc1
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%arrayidx = getelementptr inbounds float* %b, i32 %o
%0 = load float* %arrayidx, align 4
ret float %0
}
define double @foo1(double* nocapture %b, i32 %o) nounwind readonly {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo1:
; MIPS32R1: sll $[[T1:[0-9]+]], $5, 3
; MIPS32R1: addu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS32R1: ldc1 $f0, 0($[[T3]])
; MIPS32R2: sll $[[T1:[0-9]+]], $5, 3
; MIPS32R2: ldxc1 $f0, $[[T1]]($4)
; MIPS32R6: sll $[[T1:[0-9]+]], $5, 3
; MIPS32R6: addu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS32R6: ldc1 $f0, 0($[[T3]])
; MIPS4: sll $[[T0:[0-9]+]], $5, 0
; MIPS4: dsll $[[T1:[0-9]+]], $[[T0]], 3
; MIPS4: ldxc1 $f0, $[[T1]]($4)
; MIPS64R6: sll $[[T0:[0-9]+]], $5, 0
; MIPS64R6: dsll $[[T1:[0-9]+]], $[[T0]], 3
; MIPS64R6: daddu $[[T3:[0-9]+]], $4, $[[T1]]
; MIPS64R6: ldc1 $f0, 0($[[T3]])
[mips] Add NaCl target and forbid indexed loads and stores for it This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 llvm-svn: 200855
2014-02-05 18:19:30 +01:00
; CHECK-NACL-NOT: ldxc1
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%arrayidx = getelementptr inbounds double* %b, i32 %o
%0 = load double* %arrayidx, align 8
ret double %0
}
define float @foo2(i32 %b, i32 %c) nounwind readonly {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo2:
; luxc1 did not exist in MIPS32r1
; MIPS32R1-NOT: luxc1
; luxc1 is a misnomer since it aligns the given pointer downwards and performs
; an aligned load. We mustn't use it to handle unaligned loads.
; MIPS32R2-NOT: luxc1
; luxc1 was removed in MIPS32r6
; MIPS32R6-NOT: luxc1
; MIPS4-NOT: luxc1
; luxc1 was removed in MIPS64r6
; MIPS64R6-NOT: luxc1
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
%0 = load float* %arrayidx1, align 1
ret float %0
}
define void @foo3(float* nocapture %b, i32 %o) nounwind {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo3:
; MIPS32R1-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS32R1-DAG: swc1 $[[T0]], 0($[[T1]])
; MIPS32R2: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R2: swxc1 $[[T0]], ${{[0-9]+}}($4)
; MIPS32R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS32R6-DAG: swc1 $[[T0]], 0($[[T1]])
; MIPS4: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS4: swxc1 $[[T0]], ${{[0-9]+}}($4)
; MIPS64R6-DAG: lwc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS64R6-DAG: swc1 $[[T0]], 0($[[T1]])
[mips] Add NaCl target and forbid indexed loads and stores for it This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 llvm-svn: 200855
2014-02-05 18:19:30 +01:00
; CHECK-NACL-NOT: swxc1
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%0 = load float* @gf, align 4
%arrayidx = getelementptr inbounds float* %b, i32 %o
store float %0, float* %arrayidx, align 4
ret void
}
define void @foo4(double* nocapture %b, i32 %o) nounwind {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo4:
; MIPS32R1-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R1-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS32R1-DAG: sdc1 $[[T0]], 0($[[T1]])
; MIPS32R2: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R2: sdxc1 $[[T0]], ${{[0-9]+}}($4)
; MIPS32R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS32R6-DAG: addu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS32R6-DAG: sdc1 $[[T0]], 0($[[T1]])
; MIPS4: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS4: sdxc1 $[[T0]], ${{[0-9]+}}($4)
; MIPS64R6-DAG: ldc1 $[[T0:f0]], 0(${{[0-9]+}})
; MIPS64R6-DAG: daddu $[[T1:[0-9]+]], $4, ${{[0-9]+}}
; MIPS64R6-DAG: sdc1 $[[T0]], 0($[[T1]])
[mips] Add NaCl target and forbid indexed loads and stores for it This patch adds NaCl target for Mips. It also forbids indexed loads and stores if the target is NaCl. Patch by Sasa Stankovic. Differential Revision: http://llvm-reviews.chandlerc.com/D2690 llvm-svn: 200855
2014-02-05 18:19:30 +01:00
; CHECK-NACL-NOT: sdxc1
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%0 = load double* @gd, align 8
%arrayidx = getelementptr inbounds double* %b, i32 %o
store double %0, double* %arrayidx, align 8
ret void
}
define void @foo5(i32 %b, i32 %c) nounwind {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo5:
; MIPS32R1-NOT: suxc1
; MIPS32R2-NOT: suxc1
; MIPS32R6-NOT: suxc1
; MIPS4-NOT: suxc1
; MIPS64R6-NOT: suxc1
Add support for floating point base register + offset register addressing mode load and store instructions. llvm-svn: 151611
2012-02-28 03:55:02 +01:00
%0 = load float* @gf, align 4
%arrayidx1 = getelementptr inbounds [4 x %struct.S]* @s, i32 0, i32 %b, i32 0, i32 %c
store float %0, float* %arrayidx1, align 1
ret void
}
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
define double @foo6(i32 %b, i32 %c) nounwind readonly {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo6:
; MIPS32R1-NOT: luxc1
; MIPS32R2-NOT: luxc1
; MIPS32R6-NOT: luxc1
; MIPS4-NOT: luxc1
; MIPS64R6-NOT: luxc1
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
%0 = load double* %arrayidx1, align 1
ret double %0
}
define void @foo7(i32 %b, i32 %c) nounwind {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo7:
; MIPS32R1-NOT: suxc1
; MIPS32R2-NOT: suxc1
; MIPS32R6-NOT: suxc1
; MIPS4-NOT: suxc1
; MIPS64R6-NOT: suxc1
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
%0 = load double* @gd, align 8
%arrayidx1 = getelementptr inbounds [4 x %struct.S2]* @s2, i32 0, i32 %b, i32 0, i32 %c
store double %0, double* %arrayidx1, align 1
ret void
}
define float @foo8() nounwind readonly {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo8:
; MIPS32R1-NOT: luxc1
; MIPS32R2-NOT: luxc1
; MIPS32R6-NOT: luxc1
; MIPS4-NOT: luxc1
; MIPS64R6-NOT: luxc1
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
%0 = load float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
ret float %0
}
define void @foo9(float %f) nounwind {
entry:
[mips][mips64r6] [sl][duw]xc1 are not available on MIPS32r6/MIPS64r6 Summary: Folded mips64-fp-indexed-ls.ll into fp-indexed-ls.ll. To do so, the zext's in mips64-fp-indexed-ls.ll were changed to implicit sign extensions (performed by getelementptr). This does not affect the purpose of the test. Depends on D4004 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4110 llvm-svn: 210784
2014-06-12 16:19:28 +02:00
; ALL-LABEL: foo9:
; MIPS32R1-NOT: suxc1
; MIPS32R2-NOT: suxc1
; MIPS32R6-NOT: suxc1
; MIPS4-NOT: suxc1
; MIPS64R6-NOT: suxc1
Fix bugs which were introduced when support for base+index floating point loads and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
2012-03-01 23:12:30 +01:00
store float %f, float* getelementptr inbounds (%struct.S3* @s3, i32 0, i32 1), align 1
ret void
}
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