2012-11-30 20:15:10 +01:00
|
|
|
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -march=ppc32 -mattr=+altivec | FileCheck %s
|
2006-04-18 05:22:16 +02:00
|
|
|
|
2008-02-19 09:07:33 +01:00
|
|
|
define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
|
|
|
|
%tmp = load <4 x i32>* %X ; <<4 x i32>> [#uses=1]
|
|
|
|
%tmp2 = load <4 x i32>* %Y ; <<4 x i32>> [#uses=1]
|
|
|
|
%tmp3 = mul <4 x i32> %tmp, %tmp2 ; <<4 x i32>> [#uses=1]
|
|
|
|
ret <4 x i32> %tmp3
|
2006-04-18 05:22:16 +02:00
|
|
|
}
|
2013-07-13 22:38:47 +02:00
|
|
|
; CHECK-LABEL: test_v4i32:
|
2012-11-30 14:05:44 +01:00
|
|
|
; CHECK: vmsumuhm
|
|
|
|
; CHECK-NOT: mullw
|
2006-04-18 05:22:16 +02:00
|
|
|
|
2008-02-19 09:07:33 +01:00
|
|
|
define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
|
|
|
|
%tmp = load <8 x i16>* %X ; <<8 x i16>> [#uses=1]
|
|
|
|
%tmp2 = load <8 x i16>* %Y ; <<8 x i16>> [#uses=1]
|
|
|
|
%tmp3 = mul <8 x i16> %tmp, %tmp2 ; <<8 x i16>> [#uses=1]
|
|
|
|
ret <8 x i16> %tmp3
|
2006-04-18 05:54:50 +02:00
|
|
|
}
|
2013-07-13 22:38:47 +02:00
|
|
|
; CHECK-LABEL: test_v8i16:
|
2012-11-30 14:05:44 +01:00
|
|
|
; CHECK: vmladduhm
|
|
|
|
; CHECK-NOT: mullw
|
2006-04-18 05:54:50 +02:00
|
|
|
|
2008-02-19 09:07:33 +01:00
|
|
|
define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
|
|
|
|
%tmp = load <16 x i8>* %X ; <<16 x i8>> [#uses=1]
|
|
|
|
%tmp2 = load <16 x i8>* %Y ; <<16 x i8>> [#uses=1]
|
|
|
|
%tmp3 = mul <16 x i8> %tmp, %tmp2 ; <<16 x i8>> [#uses=1]
|
|
|
|
ret <16 x i8> %tmp3
|
2006-04-18 05:54:50 +02:00
|
|
|
}
|
2013-07-13 22:38:47 +02:00
|
|
|
; CHECK-LABEL: test_v16i8:
|
2012-11-30 14:05:44 +01:00
|
|
|
; CHECK: vmuloub
|
|
|
|
; CHECK: vmuleub
|
|
|
|
; CHECK-NOT: mullw
|
|
|
|
|
|
|
|
define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
|
|
|
|
%tmp = load <4 x float>* %X
|
|
|
|
%tmp2 = load <4 x float>* %Y
|
|
|
|
%tmp3 = fmul <4 x float> %tmp, %tmp2
|
|
|
|
ret <4 x float> %tmp3
|
|
|
|
}
|
|
|
|
; Check the creation of a negative zero float vector by creating a vector of
|
|
|
|
; all bits set and shifting it 31 bits to left, resulting a an vector of
|
|
|
|
; 4 x 0x80000000 (-0.0 as float).
|
2013-07-13 22:38:47 +02:00
|
|
|
; CHECK-LABEL: test_float:
|
2012-11-30 20:15:10 +01:00
|
|
|
; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
|
|
|
|
; CHECK: vslw {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
|
2012-11-30 14:05:44 +01:00
|
|
|
; CHECK: vmaddfp
|